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ISL6610 Datasheet(PDF) 8 Page - Intersil Corporation |
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ISL6610 Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 11 page 8 FN6395.0 November 22, 2006 Application Information MOSFET and Driver Selection The parasitic inductances of the PCB and of the power devices’ packaging (both upper and lower MOSFETs) can cause serious ringing, exceeding absolute maximum rating of the devices. The negative ringing at the edges of the PHASE node could increase the bootstrap capacitor voltage through the internal bootstrap diode, and in some cases, it may overstress the upper MOSFET driver. Careful layout, proper selection of MOSFETs and packaging, as well as the proper driver can go a long way toward minimizing such unwanted stress. The selection of D2-PAK, or D-PAK packaged MOSFETs, is a much better match (for the reasons discussed) for the ISL6610A with a phase resistor, as shown in Figure 5. Low- profile MOSFETs, such as Direct FETs and multi-SOURCE leads devices (SO-8, LFPAK, PowerPAK), have low parasitic lead inductances and can be driven by either ISL6610 or ISL6610A (assuming proper layout design). The ISL6610, missing the 3 Ω integrated BOOT resistor, typically yields slightly higher efficiency than the ISL6610A. Layout Considerations A good layout helps reduce the ringing on the switching node (PHASE) and significantly lower the stress applied to the output drives. The following advice is meant to lead to an optimized layout and performance: • Keep decoupling loops (VCC-GND, PVCC-PGND and BOOT-PHASE) short and wide, at least 25 mils. Avoid using vias on decoupling components other than their ground terminals, which should be on a copper plane with at least two vias. • Minimize trace inductance, especially on low-impedance lines. All power traces (UGATE, PHASE, LGATE, PGND, PVCC, VCC, GND) should be short and wide, at least 25 mils. Try to place power traces on a single layer, otherwise, two vias on interconnection are preferred where possible. For no connection (NC) pins on the QFN part, connect it to the adjacent net (LGATE2/PHASE2) can reduce trace inductance. • Shorten all gate drive loops (UGATE-PHASE and LGATE- PGND) and route them closely spaced. • Minimize the inductance of the PHASE node. Ideally, the source of the upper and the drain of the lower MOSFET should be as close as thermally allowable. • Minimize the current loop of the output and input power trains. Short the source connection of the lower MOSFET to ground as close to the transistor pin as feasible. Input capacitors (especially ceramic decoupling) should be placed as close to the drain of upper and source of lower MOSFETs as possible. • Avoid routing relatively high impedance nodes (such as PWM and ENABLE lines) close to high dV/dt UGATE and PHASE nodes. In addition, connecting the thermal pad of the QFN package to the power ground through multiple vias, or placing a low noise copper plane (such as power ground) underneath the SOIC part is recommended. This is to improve heat dissipation and allow the part to achieve its full thermal potential. Upper MOSFET Self Turn-On Effects At Startup Should the driver have insufficient bias voltage applied, its outputs are floating. If the input bus is energized at a high dV/dt rate while the driver outputs are floating, due to the self-coupling via the internal CGD of the MOSFET, the UGATE could momentarily rise up to a level greater than the threshold voltage of the MOSFET. This could potentially turn on the upper switch and result in damaging inrush energy. FIGURE 3. TYPICAL UPPER-GATE DRIVE TURN-ON PATH FIGURE 4. TYPICAL LOWER-GATE DRIVE TURN-ON PATH FIGURE 5. PHASE RESISTOR TO MINIMIZE SERIOUS NEGATIVE PHASE SPIKE Q1 D S G RGI1 RG1 BOOT RHI1 CDS CGS CGD RLO1 PHASE PVCC UGATE PVCC Q2 D S G RGI2 RG2 RHI2 CDS CGS CGD RLO2 GND LGATE Q1 D S G RPH=1-2Ω BOOT RHI1 RLO1 PHASE PVCC UGATE ISL6610, ISL6610A |
Similar Part No. - ISL6610 |
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Similar Description - ISL6610 |
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