8

TIMING CHARACTERISTICS

125

-

-

MSPS

100

-

-

MSPS

CLK (Note 3)

5

-

-

ns

Maximum Parallel Write Rate

Rate of WR

50

-

-

MSPS

(Note 3)

5

-

-

ns

Between DATA and WR (Note 3)

10

-

-

ns

Between DATA and WR (Note 3)

0

-

-

ns

Between ADDR and WR (Note 3)

12

-

-

ns

Between ADDR and WR (Note 3)

0

-

-

ns

(Note 3)

5

-

-

ns

Between UPDATE and CLK (Note 3)

2

-

-

ns

Between UPDATE and CLK (Note 3)

4

-

-

ns

After UPDATE, before analog output change, if asserted after

writing to the control registers

-14

-

Clock

Cycles

After UPDATE, before analog output change, if asserted before

writing to the control registers

-11

-

Clock

Cycles

PH(1:0) (Note 3)

5

-

-

ns

Between PH(1:0) change and CLK (Note 3)

2

-

-

ns

Between PH(1:0) change and CLK (Note 3)

4

-

-

ns

Between PH(1:0) change and analog output change

-

12

-

Clock

Cycles

ENOFR (Note 3)

5

-

-

ns

Between ENOFR and CLK (Note 3)

2

-

-

ns

Between ENOFR and CLK (Note 3)

4

-

-

ns

After ENOFR, before analog output change

-

14

-

Clock

Cycles

WE (Note 3)

5

-

-

ns

Between WE and WR (Note 3)

2

-

-

ns

Between WE and WR (Note 3)

4

-

-

ns

RESET (Note 3)

5

-

-

ns

Between RESET and CLK

-

2

-

ns

After RESET, before analog output reflects reset values

-

11

-

Clock

Cycles

After RESET, before the control registers can be written to

-

1

-

Clock

Cycles

PARAMETER

TEST CONDITIONS

HSP45314

UNITS

MIN

TYP

MAX

HSP45314