HI5860IB datasheet(4/10 Pages) INTERSIL

Part #	HI5860IB

Description	12-Bit, 130MSPS, High Speed D/A Converter

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Manufacturer	INTERSIL [Intersil Corporation]

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4

FN4654.6

May 4, 2005

Absolute Maximum Ratings

Thermal Information

Digital Supply Voltage DVDD to DCOM . . . . . . . . . . . . . . . . . +5.5V

Analog Supply Voltage AVDD to ACOM. . . . . . . . . . . . . . . . . . +5.5V

Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V

Digital Input Voltages (D11-D0, CLK, SLEEP) . . . . . . . DVDD + 0.3V

Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AVDD + 0.3V

Analog Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C°C

Thermal Resistance (Typical, Note 1)

θJA(°C/W)

SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

75

TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .

100

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C

Maximum Storage Temperature Range . . . . . . . . . . -65°C to 150°C

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1.

θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

AVDD = DVDD = +5V (except where otherwise noted), VREF = Internal 1.2V, IOUTFS = 20mA,

TA = 25°C for All Typical Value

PARAMETER

TEST CONDITIONS

TA = -40°C TO 85°C

UNITS

MIN

TYP

MAX

SYSTEM PERFORMANCE

Resolution

12

-

Bits

Integral Linearity Error, INL

“Best Fit” Straight Line (Note 8)

-2.0

±0.5

+2.0

LSB

Differential Linearity Error, DNL

(Note 8)

-1.0

±0.5

+1.0

LSB

Offset Error, IOS

(Note 8)

-0.025

-

+0.025

% FSR

Offset Drift Coefficient

(Note 8)

-

0.1

-

ppm

FSR/°C°

C

Full Scale Gain Error, FSE

With External Reference (Notes 2, 8)

-10

±2

+10

% FSR

With Internal Reference (Notes 2, 8)

-10

±1

+10

% FSR

Full Scale Gain Drift

With External Reference (Note 8)

-

±50

-

ppm

FSR/°C

With Internal Reference (Note 8)

-

±100

-

ppm

FSR/°C

Full Scale Output Current, IFS

2

-

20

mA

Output Voltage Compliance Range

(Note 3, 8)

-0.3

-

1.25

V

DYNAMIC CHARACTERISTICS

Maximum Clock Rate, fCLK

(Note 3)

130

-

MHz

Output Settling Time, (tSETT)

±0.05% (±2 LSB) (Note 8)

-

35

-

ns

Singlet Glitch Area (Peak Glitch)

RL = 25Ω (Note 8)

-

5

-

pV•s

Output Rise Time

Full Scale Step

-

2.5

-

ns

Output Fall Time

Full Scale Step

-

2.5

-

ns

Output Capacitance

-

10

-

pF

Output Noise

IOUTFS = 20mA

-

50

-

pA/

√Hz

IOUTFS = 2mA

-

30

-

pA/

√Hz

AC CHARACTERISTICS

+5V Power Supply

Spurious Free Dynamic Range,

SFDR Within a Window

fCLK = 100MSPS, fOUT = 20.2MHz, 10MHz Span (Notes 4, 8)

-

77

-

dBc

fCLK = 100MSPS, fOUT = 5.04MHz, 4MHz Span (Notes 4, 8)

-

95

-

dBc

fCLK = 50MSPS, fOUT = 5.02MHz, 2MHz Span (Notes 4, 8)

-

95

-

dBc

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