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AM49DL640BH85IT Datasheet(PDF) 10 Page - SPANSION |
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AM49DL640BH85IT Datasheet(HTML) 10 Page - SPANSION |
10 / 63 page 8 Am49DL640BH December 5, 2003 ADV ANCE I N FO RMAT I O N CE#f = Chip Enable (Flash) CE1#s = Chip Enable 1 (pSRAM) CE2s = Chip Enable 2 (pSRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output UB#s = Upper Byte Control (pSRAM) LB#s = Lower Byte Control (pSRAM) CIOf = I/O Configuration (Flash) CIOf = VIH = Word mode (x16), CIOf = VIL = Byte mode (x8) RESET# = Hardware Reset Pin, Active Low WP#/ACC = Hardware Write Protect/ Acceleration Pin (Flash) VCCf = Flash 3.0 volt-only single power sup- ply (see Product Selector Guide for speed options and voltage supply tolerances) VCCs = pSRAM Power Supply VSS = Device Ground (Common) NC = Pin Not Connected Internally LOGIC SYMBOL 21 16 or 8 DQ15–DQ0 A20–A0 CE#f OE# WE# RESET# UB#s RY/BY# WP#/ACC SA A21, A-1 LB#s CIOf CE1#s CE2s |
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