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2

Unit Loading/Fan Out

Function Table

H

= HIGH Voltage Level

L

= LOW Voltage Level

X

= Irrelevant

 = LOW-to-HIGH Transition

Note 1: The data output functions may be enabled or disabled by various signals at the G and DIR Inputs. Data input functions are always enabled;

i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the clock inputs.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

Pin Names

Description

U.L.

HIGH/LOW

Data Register A Inputs/

3.5/1.083

70

µA/−650 µA

3-STATE Outputs

600/106.6 (80)

−12 mA/64 mA (48 mA)

Data Register B Inputs/

3.5/1.083

70

µA/−650 µA

3-STATE Outputs

600/106.6 (80)

−12 mA/64 mA (48 mA)

CPAB, CPBA

Clock Pulse Inputs

1.0/1.0

20

µA/−0.6 mA

SAB, SBA

Select Inputs

1.0/1.0

20

µA/−0.6 mA

G

Output Enable Input

1.0/1.0

20

µA/−0.6 mA

DIR

Direction Control Input

1.0/1.0

20

µA/−0.6 mA

Inputs

Data I/O (Note 1)

Function

G

DIR

CPAB CPBA

SAB

SBA

H

X

H or L H or L

X

X

Isolation

HX



X

X

X

Input

Input

HX

X



X

X

LH

X

X

L

X

LH



X

L

X

Input

Output

L

H

H or L

X

H

X

LH



X

H

X

L

L

XXX

L

LL

X



X

L

Output

Input

L

L

X

H or L

X

H

LL

X



X

H