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HMP8156A Datasheet(PDF) 5 Page - Intersil Corporation |
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HMP8156A Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 34 page  5 4343.4 November 4, 2005 The last pixel output of the overlay uses 87.5% overlay color plus 12.5% pixel color. The next output uses 12.5% overlay color plus 87.5% pixel color. Additional outputs use 100% pixel color. When going from one overlay color to another, mixing starts one pixel before the selection of the new overlay color, and uses 12.5% new overlay color plus 87.5% old overlay color. The next output is aligned with the selection of the new overlay color and uses 87.5% new overlay color plus 12.5% old overlay color. Additional outputs use 100% new overlay color. Overlay Mixing: No Mixing With no overlay mixing selected, whenever the OL0-OL2 inputs are non-zero, the overlay color is displayed. The M0 and M1 inputs are ignored, and no internal mixing is done. Essentially, this is a hard switch between overlay and pixel data. In this mode, there is no minimum number of pixels an overlay color or pixel color must be selected. 2X Upscaling Processing Following overlay processing, 2X upscaling may optionally be applied to the pixel data. In this mode, the HMP8154/HMP8156A accepts NTSC (PAL) SIF resolution video at 59.94 (50) frames per second and generates standard interlaced video with 262.5 (312.5) lines per field at 59.94 (50) fields per second. This mode of operation allows SIF video to be upscaled to full resolution and recorded on a VCR or displayed on a TV. SIP upscaling may be used to simplify PC to TV applications. The input pixel data rate is reduced by half when 2X upscaling is enabled. The color space conversion generates, and the overlay mixer uses, 2:2:2 YCbCr data instead of 4:4:4 data. For rectangular pixel NTSC and PAL video, the input rate is 6.75MHz during the active portion of each line instead of 13.5MHz. Example SIF input resolutions and resulting output resolutions are shown in Table 4. The HMP8154/HMP8156A performs horizontal 2X upscaling by linear interpolation. The vertical scaling is done by line duplication. For typical line duplication, the same frame of SIF pixel input data is used for both the odd and even fields. Note that a frame of SIF size input has about the same number of lines as a field of full size input. After 2X upscaling, the input is 4:4:4 YCbCr data ready for video processing. Flicker filtering is not available when 2X upscaling is enabled. Flicker Filter Processing Following overlay processing, vertical flicker filtering may optionally be applied to the pixel data by the HMP8154. The HMP8156A does not provide flicker filter capability. In flicker filter mode, the HMP8154 accepts non-interlaced NTSC (PAL) full resolution video with 525 (625) lines per frame at 59.94 (50) frames per second. It generates standard interlaced video with 262.5 (312.5) lines per field at 59.94 (50) fields per second. Each frame of non-interlaced video is vertically low pass filtered and used to generate either an odd or even field of video. This mode of operation reduces flickering caused by image details that are less than two pixels high. Since an entire frame of input is used to generate one field of output, the input pixel data rate is doubled when the flicker filter is enabled. The encoder must receive two lines of data during each line time. For rectangular pixel NTSC and PAL video, the input rate is 27.0MHz during the active portion of each line instead of 13.5MHz. Because of the high input data rate, 8-bit YCbCr and BT.656 input formats and 2X upscaling of SIF input may not be used when the flicker filter is enabled. The HMP8154 uses internal line stores and a 3 tap FIR filter to reduce flickering. The filter coefficients are 0.25, 0.5, and 0.25. At the start and end of each field, the coefficients are modified to compensate for the insufficient number of lines available for processing. When filtering is enabled, there is an additional two line time delay through the encoder. After flicker filtering, the input is 4:4:4 YCbCr data ready for video processing. 2X upscaling is not available when the flicker filter is enabled. Pixel Input and Control Signal Timing The pixel input timing and the video control signal input/output timing of the HMP8154/HMP8156A depend on the part’s operating mode. The periods when the encoder samples its inputs and generates its outputs are summarized in Table 5. Figures 1-12 show the timing of CLK, CLK2, BLANK, and the pixel and overlay input data with respect to each other. BLANK may be an input or an output; the figures show both. When it is an input, BLANK must arrive coincident with the pixel and overlay input data; all are sampled at the same time. When BLANK is an output, its timing with respect to the pixel and overlay inputs depends on the blank timing select bit in the timing_I/O_1 register. If the bit is cleared, the HMP8154/HMP8156A deasserts BLANK one CLK cycle before it samples the pixel and overlay inputs. As shown in the timing figures, the encoder samples the inputs 1-7 CLK2 periods after negating BLANK, depending on the operating mode. If the bit is set, the encoder deasserts BLANK during the same CLK cycle in which it samples the input data. In effect, the input data must arrive one CLK cycle earlier than when the bit is cleared. This mode is not shown in the figures. TABLE 4. TYPICAL RESOLUTIONS FOR 2X UPSCALING INPUT ACTIVE RESOLUTION OUTPUT ACTIVE RESOLUTION 352 x 240 352 x 288 320 x 240 384 x 288 704 x 480 704 x 576 640 x 480 768 x 576 HMP8154, HMP8156A |
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