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HC55171IM Datasheet(PDF) 7 Page - Intersil Corporation |
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HC55171IM Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 20 page 7 Functional Diagram The truth table for the internal logic of the HC55171 is provided in the above table. This family of ringing SLICs can be configured to support traditional unbalanced ringing and thru SLIC balanced ringing. Refer to the HC5509A1R3060 for unbalanced ringing application information. The device operating states used by thru SLIC ringing applications are loop power denial and normal feed. During loop power denial, the tip and ring amplifiers are disabled (high impedance) and the DC voltage of each amplifier approaches ground. The SLIC will not provide current to the subscriber loop during this mode and will not detect loop closure. Voice transmission occurs during the normal loop feed mode. During normal loop feed the SLIC is completely operational and performs all transmission and supervisory functions. Power Dissipation Careful thermal design is required to guarantee that the maximum junction temperature of 150oC of the device is not exceeded. The junction temperature of the SLIC can be calculated using: Where TA is maximum ambient temperature and θJA is junction to air thermal resistance (and is package dependent). The entire term in parentheses yields the SLIC power dissipation. The power dissipation of the subscriber loop does not contribute to device junction temperature and is subtracted from the power dissipation term. Operating at 85oC, the maximum PLCC SLIC power dissipation is 1.18W. Likewise, the maximum SOIC SLIC power dissipation is 0.92W. R R VREF R VRX OUT 1 R/20 R/2 TIP TA R 2R 2R R 90K RING RA 4.5K 25K 25K 100K 100K 4.5K 90K RF 25 17 12 +2V TF 14 RF 15 16 26 3 OP AMP VRING VTX GM 28 11 RF2 BIAS NETWORK AGND VCC TSD GK RFC SH F0 F1 RS ALM RTD SHD TST VBAT -IN 1 13 24 19 2 1 TF BGND 22 27 4 5 6 9 20 21 7 8 10 R = 108k Ω R R 100K 100K 90K 18 RTI NU ILMT SENSE SENSE 1 RING SENSE 2 RDI RDO + - + - THERM LTD SHD RTD FAULT DET + - REF VB/2 + - + - + - HC55171 DEVICE TRUTH TABLE F1 F0 STATE 0 0 Loop power Denial Active 0 1 Power Down Latch RESET, Power on RESET 1 0 RD Active 1 1 Normal Loop feed T J T A θ JA ICC VCC I BAT VBAT I LOOP () 2 R LOOP • () – + () + = (EQ. 1) HC55171 |
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