7

Detailed Description

Theory of Operation

The HI5905 is a 14-bit fully differential sampling pipeline A/D

converter with digital error correction. Figure 8 depicts the

circuit for the front end differential-in-differential-out sample-

and-hold (S/H). The switches are controlled by an internal

clock which is a non-overlapping two phase signal,

φ

φ

phase,

φ

are discharged to analog ground. At the falling edge of

φ

1

the input signal is sampled on the bottom plates of the

sampling capacitors. In the next clock phase,

φ

bottom plates of the sampling capacitors are connected

together and the holding capacitors are switched to the op-

amp output nodes. The charge then redistributes between

output is a fully-differential, sampled-data representation of

the analog input. The circuit not only performs the sample-

and-hold function but will also convert a single-ended input

to a fully-differential output for the converter core. During the

components result in a typical full power input bandwidth of

100MHz for the converter.

As illustrated in the functional block diagram and the timing

diagram in Figure 1, four identical pipeline subconverter stages,

each containing a four-bit flash converter, a four-bit digital-to-

analog converter and an amplifier with a voltage gain of 8,

follow the S/H circuit with the fifth stage being only a 4-bit flash

converter. Each converter stage in the pipeline will be sampling

in one phase and amplifying in the other clock phase. Each

individual sub-converter clock signal is offset by 180 degrees

from the previous stage clock signal, with the result that

alternate stages in the pipeline will perform the same operation.

The output of each of the four-bit subconverter stages is a

four-bit digital word containing a supplementary bit to be used

by the digital error correction logic. The output of each

subconverter stage is input to a digital delay line which is

controlled by the internal sampling clock. The function of the

digital delay line is to time align the digital outputs of the four

identical four-bit subconverter stages with the corresponding

output of the fifth stage flash converter before applying the

Pin Descriptions

PIN #

NAME

DESCRIPTION

1

NC

No Connection

2

NC

No Connection

3

Digital Ground

4

NC

No Connection

5

Analog Supply (5.0V)

6

Analog Ground

7

NC

No Connection

8

NC

No Connection

9

Positive Analog Input

10

Negative Analog Input

11

DC Bias Voltage Output

12

NC

No Connection

13

Reference Voltage Output

14

Reference Voltage Input

15

Analog Ground

16

Analog Supply (5.0V)

17

NC

No Connection

18

D13

Data Bit 11 Output (MSB)

19

D12

Data Bit 11 Output

20

D11

Data Bit 11 Output

21

D10

Data Bit 10 Output

22

NC

No Connection

23

NC

No Connection

24

D9

Data Bit 9 Output

25

D8

Data Bit 8 Output

26

Digital Ground

27

Digital Supply (5.0V)

28

NC

No Connection

29

D7

Data Bit 7 Output

30

D6

Data Bit 6 Output

31

D5

Data Bit 5 Output

32

D4

Data Bit 4 Output

33

D3

Data Bit 3 Output

34

NC

No Connection

35

NC

No Connection

36

D2

Data Bit 2 Output

37

D1

Data Bit 1 Output

38

D0

Data Bit 0 Output (LSB)

39

NC

No Connection

40

CLK

Input Clock

41

Digital Supply (5.0V)

42

Digital Ground

43

Digital Supply (5.0V)

44

NC

No Connection

φ

1

φ

1

φ

2

φ

1

φ

1

φ

1

φ

1

+

-

FIGURE 8. ANALOG INPUT SAMPLE-AND-HOLD

HI5905