tm

March 2007

©1993 Fairchild Semiconductor Corporation

www.fairchildsemi.com

74ABT373 Rev. 1.4

74ABT373

Octal Transparent Latch with 3-STATE Outputs

Features

32mA

loads

dynamic threshold performance

power up and power down

General Description

The ABT373 consists of eight latches with 3-STATE

outputs for bus organized system applications. The flip-

flops appear transparent to the data when Latch Enable

(LE) is HIGH. When LE is LOW, the data that meets the

setup times is latched. Data appears on the bus when

the Output Enable (OE) is LOW. When OE is HIGH the

bus output is in the high impedance state.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

Pb-Free package per JEDEC J-STD-020B.

Connection Diagram

Pin Descriptions

Order Number

Package

Number

Package Description

74ABT373CSC

M20B

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

74ABT373CSJ

M20D

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ABT373CMSA

MSA20

20-Lead Shrink Small Outline Package (SSOP), JEDEC MO-150, 5.3mm Wide

74ABT373CMTC

MTC20

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

Pin Names

Description

Data Inputs

LE

Latch Enable Input (Active HIGH)

OE

Output Enable Input (Active LOW)

3-STATE Latch Outputs