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COM20020I3VLJP Datasheet(PDF) 11 Page - SMSC Corporation |
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COM20020I3VLJP Datasheet(HTML) 11 Page - SMSC Corporation |
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11 / 69 page  5Mbps ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM SMSC COM20020I 3.3V Rev.E Page 11 Revision 09-11-06 DATASHEET Chapter 4 Protocol Description 4.1 Network Protocol Communication on the network is based on a token passing protocol. Establishment of the network configuration and management of the network protocol are handled entirely by the COM20020I 3V's internal microcoded sequencer. A processor or intelligent peripheral transmits data by simply loading a data packet and its destination ID into the COM20020I 3V's internal RAM buffer, and issuing a command to enable the transmitter. When the COM20020I 3V next receives the token, it verifies that the receiving node is ready by first transmitting a FREE BUFFER ENQUIRY message. If the receiving node transmits an ACKnowledge message, the data packet is transmitted followed by a 16-bit CRC. If the receiving node cannot accept the packet (typically its receiver is inhibited), it transmits a Negative AcKnowledge message and the transmitter passes the token. Once it has been established that the receiving node can accept the packet and transmission is complete, the receiving node verifies the packet. If the packet is received successfully, the receiving node transmits an ACKnowledge message (or nothing if it is not received successfully) allowing the transmitter to set the appropriate status bits to indicate successful or unsuccessful delivery of the packet. An interrupt mask permits the COM20020I 3V to generate an interrupt to the processor when selected status bits become true. Figure 1 is a flow chart illustrating the internal operation of the COM20020I 3V connected to a 20 MHz crystal oscillator. 4.2 Data Rates The COM20020I 3V is capable of supporting data rates from 156.25 Kbps to 5 Mbps. The following protocol description assumes a 5 Mbps data rate. To attain the faster data rates, the clock frequency may be doubled by the internal clock multiplier (see next section). For slower data rates, an internal clock divider scales down the clock frequency. Thus all timeout values are scaled as shown in the following table: Example: IDLE LINE Timeout @ 5 Mbps = 41 μs. IDLE LINE Timeout for 156.2 Kbps is 41 μs * 32 = 1.3 ms INTERNAL CLOCK FREQUENCY CLOCK PRESCALER DATA RATE TIMEOUT SCALING FACTOR (MULTIPLY BY) 40 MHz Div. by 8 5 Mbps 1 20 MHz Div. by 8 Div. by 16 Div. by 32 Div. by 64 Div. by 128 2.5 Mbps 1.25 Mbps 625 Kbps 312.5 Kbps 156.25 Kbps 2 4 8 16 32 4.2.1 Selecting Clock Frequencies Above 2.5 Mbps To realize a 5 Mbps network, an external 40 MHz clock must be input. However, since 40 MHz is near the frequency of FM radio band, it is not practical for use for noise emission reasons. Therefore, higher frequency clocks are generated from the 20 MHz crystal as selected through two bits in the Setup2 register, CKUP as shown below. The selected clock is supplied to the ARCNET controller. CKUP CLOCK FREQUENCY (DATA RATE) 0 20 MHz (Up to 2.5Mbps) Default (Bypass) 1 40 MHz (Up to 5Mbps) This clock multiplier is powered-down (bypassed) on default. After changing the CKUP bit, the ARCNET core operation is stopped and the internal PLL in the clock generator is awakened and it starts to generate the 40 MHz. The lock out time of the internal PLL is 8uSec typically. After more than 8 μsec (this wait time is defined as 1 msec in this data sheet), it is necessary to write command data '18H' to the command register to re-start the ARCNET core operation. This clock generator is called “clock multiplier”. Changing the CKUP bit must be one time or less after releasing hardware reset. |
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