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HFA1145 Datasheet(PDF) 5 Page - Intersil Corporation |
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HFA1145 Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 13 page 5 FN3955.5 June 1, 2006 Application Information Optimum Feedback Resistor Although a current feedback amplifier’s bandwidth dependency on closed loop gain isn’t as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier’s unique relationship between bandwidth and RF. All current feedback amplifiers require a feedback resistor, even for unity gain applications, and RF, in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier’s bandwidth is inversely proportional to RF. The HFA1145 design is optimized for RF = 510Ω at a gain of +2. Decreasing RF decreases stability, resulting in excessive peaking and overshoot (Note: Capacitive feedback will cause the same problems due to the feedback impedance decrease at higher frequencies). At higher gains, however, the amplifier is more stable so RF can be decreased in a trade-off of stability for bandwidth. The table below lists recommended RF values for various gains, and the expected bandwidth. For a gain of +1, a resistor (+RS) in series with +IN is required to reduce gain peaking and increase stability. Non-inverting Input Source Impedance For best operation, the DC source impedance seen by the non-inverting input should be ≥50Ω. This is especially important in inverting gain configurations where the non- inverting input would normally be connected directly to GND. DISABLE Input TTL Compatibility The HFA1145 derives an internal GND reference for the digital circuitry as long as the power supplies are symmetrical about GND. With symmetrical supplies the digital switching threshold (VTH = (VIH + VIL)/2 = (2.0 + 0.8)/2) is 1.4V, which ensures the TTL compatibility of the DISABLE input. If asymmetrical supplies (e.g. +10V, 0V) are utilized, the switching threshold becomes: and the VIH and VIL levels will be VTH ± 0.6V, respectively. DISABLE Input Logic High Current VDISABLE = 5V A Full - 1 15 μA Output Disable Time (Note 6) VIN = ±1V, VDISABLE = 2.4V to 0V B25 - 35 - ns Output Enable Time (Note 6) VIN = ±1V, VDISABLE = 0V to 2.4V B 25 - 180 - ns Disabled Output Capacitance VDISABLE = 0V B 25 - 2.5 - pF Disabled Output Leakage VDISABLE = 0V, VIN = 2V, VOUT = ±3V AFull - 3 10 μA Off Isolation (VDISABLE = 0V, VIN = 1VP-P, Note 6) At 5MHz B 25 - -75 - dB At 25MHz B 25 - -60 - dB POWER SUPPLY CHARACTERISTICS Power Supply Range C 25 ±4.5 - ±5.5 V Power Supply Current (Note 6) A 25 - 5.8 6.1 mA A Full - 5.9 6.3 mA NOTES: 3. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only. 4. Undershoot dominates for output signal swings below GND (e.g. 0.5VP-P), yielding a higher overshoot limit compared to the VOUT = 0 to 0.5V condition. See the “Application Information” section for details. 5. Slew rates are asymmetrical if the output swings below GND (e.g. a bipolar signal). Positive unipolar output signals have symmetric positive and negative slew rates comparable to the +SR specification. See the “Application Information” section, and the pulse response graphs for details. 6. See Typical Performance Curves for more information. Electrical Specifications VSUPPLY = ±5V, AV = +1, RF = 510Ω, RL = 100Ω, Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS (NOTE 3) TEST LEVEL TEMP. (°C) MIN TYP MAX UNITS GAIN (ACL) RF (Ω) BANDWIDTH (MHz) -1 425 300 +1 510 (+RS = 510Ω) 270 +2 510 330 +5 200 300 +10 180 130 V TH V+ V- + 2 ------------------- 1.4V + = HFA1145 |
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