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HI1396AIL Datasheet(PDF) 5 Page - Intersil Corporation |
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HI1396AIL Datasheet(HTML) 5 Page - Intersil Corporation |
5 / 10 page 5 21 35 CLK I ECL CLK Input. 20 34 CLK Input complementary to CLK. When left open pulled down to -1.3V. Device is operable without CLK input, but use of complementary inputs of CLK and CLK is recommended to obtain stable high speed operation. 5, 16 7, 24 DGND1 - 0V Digital GND for internal circuits. 6, 15 8, 23 DGND2 - 0V Digital GND for output transistors. 4, 17 5, 30 DVEE - -5.2V Digital VEE. Internally connected to AVEE (resistance: 4Ω to 6Ω). Bypass with 0.1 µF to DGND 7 14 D0 O ECL LSB of data outputs. External pull-down resistor is required. 815 D1 Data outputs. External pull-down resistors are required. 916 D2 10 17 D3 11 18 D4 12 19 D5 13 20 D6 14 21 D7 MSB of data outputs. External pull-down resistor is required. Pin Descriptions and I/O Pin Equivalent Circuits (Continued) PIN NUMBER SYMBOL I/O STANDARD VOLTAGE LEVEL EQUIVALENT CIRCUIT DESCRIPTION DIP LCC DVEE CLK CLK DGND1 R R R R RR DVEE DGND2 DI HI1396 |
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