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AM29LV652D Datasheet(PDF) 4 Page - Advanced Micro Devices

Part No. AM29LV652D
Description  128 Megabit (16 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileIO™ Control
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Maker  AMD [Advanced Micro Devices]
Homepage  http://www.amd.com
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Am29LV652D
24961A5 May 5, 2006
D A TA
SH EE T
GENERAL DESCRIPTION
The Am29LV652D is a 128 Mbit, 3.0 Volt (3.0 V to 3.6
V) single power supply flash memory device organized
as two Am29LV065D dice in a single 63-ball FBGA
package. Each Am29LV065D is a 64 Mbit, 3.0 Volt (3.0
V to 3.6 V) single power supply flash memory device
organized as 8,388,608 bytes. Data appears on
DQ0-DQ7. The device is designed to be programmed
in-system with the standard system 3.0 volt V
CC sup-
ply. A 12.0 volt V
PP is not required for program or erase
operations. The Am29LV652D is equipped with two
CE#s for flexible selection between the two internal 64
Mb devices. The device can also be programmed in
standard EPROM programmers.
The Am29LV652D offers access times of 90 and 120
ns and is offered in a 63-ball FBGA package. To elimi-
nate bus contention the Am29LV652D device contains
two separate chip enables (CE# and CE2#). Each chip
enable (CE# or CE2#) is connected to only one of the
two dice in the Am29LV652D package. To the sys-
tem, this device is the same as two independent
Am29LV065D on the same board. The only differ-
ence is that they are now packaged together to re-
duce board space.
Each device requires only a single 3.0 Volt power
supply (3.0 V to 3.6 V) for both read and write func-
tions. Internally generated and regulated voltages are
provided for the program and erase operations.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timing. Register con-
tents serve as inputs to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also inter nally latch addresses and data
needed for the programming and erase operations.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facili-
tates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase,
the device automatically times the erase pulse widths
and verifies proper cell margin.
The VersatileI/O™ (V
IO) control allows the host sys-
tem to set the voltage levels that the device generates
at its data outputs and the voltages tolerated at its data
inputs to the same voltage level that is asserted on
V
IO. This allows the device to operate in a 3 V or 5 V
system environment as required. For voltage levels
below 3 V, contact an AMD representative for more in-
formation.
The host system can detect whether a program or
erase operation is complete by observing RY/BY#, by
reading the DQ7 (Data# Polling), or DQ6 (toggle) sta-
tus bits. After a program or erase cycle is completed,
the device is ready to read array data or accept an-
other command.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of sectors of memory.
This can be achieved in-system or via programming
equipment.
The Erase Suspend/Erase Resume feature enables
the user to put erase on hold for any period of time to
read data from, or program data to, any sector that is
not selected for erasure. True background erase can
thus be achieved.
The hardware RESET# terminates any operation in
progress and resets the internal state machine to
reading array data. RESET# may be tied to the system
reset circuitry. A system reset would thus also reset
the device, enabling the system microprocessor to
read boot-up firmware from the Flash memory device.
The device offers a standby mode as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
The accelerated program (ACC) feature allows the
system to program the device at a much faster rate.
When ACC is pulled high to V
HH, the device enters the
Unlock Bypass mode, enabling the user to reduce the
time needed to do the program operation. This feature
is intended to increase factory throughput during sys-
tem production, but may also be used in the field if de-
sired.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within a
sector simultaneously via Fowler-Nordheim tunnelling.
The data is programmed using hot electron injection.



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