EM6A9320BI-2.8 datasheet(11/17 Pages) ETRON

Part #	EM6A9320BI-2.8

Description	4M x 32 DDR SDRAM

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Manufacturer	ETRON [Etron Technology, Inc.]

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EtronTech

4Mx32 DDR SDRAM

EM6A9320

11

Rev 0.6

May. 2006

Electrical Characteristics and Recommended A.C. Operating Conditions

(VDD = 2.8V

± 5%, Ta = 0~70 °C)

2.8

3.0

3.3

3.5

Symbol

Parameter

Min

Max

Min

Max

Min

Max

Min

Max

Unit

CL = 3

3.3

10

3.3

10

3.3

10

3.5

10

CL = 4

2.86

10

3.0

10

3.3

10

3.5

10

tCK

Clock cycle time

CL = 5

2.86

5

3.0

5

3.3

5

3.5

5

ns

tCH

Clock high level width

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

tCK

tCL

Clock low level width

0.45

0.55

0.45

0.55

0.45

0.55

0.45

0.55

tCK

tDQSCK

DQS-out access time from CK,CK#

-0.6

0.6

-0.6

0.6

-0.6

0.6

-0.6

0.6

ns

tAC

Output access time from CK,CK#

-0.6

0.6

-0.6

0.6

-0.6

0.6

-0.6

0.6

ns

tDQSQ

DQS-DQ Skew

-

0.35

-

0.35

-

0.35

-

0.4

ns

tRPRE

Read preamble

0.9

1.1

0.9

1.1

0.9

1.1

0.9

1.1

tCK

tRPST

Read postamble

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

tDQSS

CK to valid DQS-in

0.85

1.15

0.85

1.15

0.85

1.15

0.85

1.15

tCK

tWPRES DQS-in setup time

0

-

0

-

0

-

0

-

ns

tWPREH DQS-in hold time

0.35

-

0.35

-

0.35

-

0.35

-

ns

tWPST

DQS write postamble

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

tDQSH

DQS in high level pulse width

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

tDQSL

DQS in low level pulse width

0.4

0.6

0.4

0.6

0.4

0.6

0.4

0.6

tCK

tIS

Address and Control input setup time

0.9

-

0.9

-

0.9

-

0.9

-

ns

tIH

Address and Control input hold time

0.9

-

0.9

-

0.9

-

0.9

-

ns

tDS

DQ & DM setup time to DQS

0.35

-

0.35

-

0.35

-

0.4

-

ns

tDH

DQ & DM hold time to DQS

0.35

-

0.35

-

0.35

-

0.4

-

ns

tHP

Clock half period

tCLMIN

or

tCHMIN

-

tCLMIN

or

tCHMIN

-

tCLMIN

or

tCHMIN

-

tCLMIN

or

tCHMIN

-

ns

tQH

Output DQS valid window

tHP -

0.35

-

tHP -

0.35

-

tHP -

0.35

-

tHP -

0.4

-

ns

tRC

Row cycle time

20

-

20

-

17

-

16

-

tCK

tRFC

Refresh row cycle time

22

-

22

-

19

-

18

-

tCK

tRAS

Row active time

14

100K

14

100K

12

100K

11

100K

tCK

tRCDRD RAS# to CAS# Delay in Read

7

-

7

-

6

-

5

-

tCK

tRCDWR RAS# to CAS# Delay in Write

5

-

5

-

4

-

3

-

tCK

tRP

Row precharge time

6

-

6

-

5

-

3

-

tCK

tRRD

Row active to Row active delay

4

-

4

-

3

-

3

-

tCK

twR

Write recovery time

3

-

3

-

3

-

3

-

tCK

tCDLR

Last data in to Read command

2

-

2

-

2

-

2

-

tCK

tCCD

Col. Address to Col. Address delay

1

-

1

-

1

-

1

-

tCK

tMRD

Mode register set cycle time

1

-

1

-

1

-

1

-

tCK

tDAL

Auto precharge write recovery + Precharge

9

-

9

-

9

-

9

-

tCK

tXSA

Self refresh exit to read command delay

200

-

200

-

200

-

200

-

tCK

tPDEX

Power down exit time

tIS +

2tCK

-

tIS +

2tCK

-

tIS +

2tCK

-

tIS +

2tCK

-

ns

tREF

Refresh interval time

-

7.8

-

7.8

-

7.8

us

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