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HI-8110SM-32 Datasheet(PDF) 2 Page - Holt Integrated Circuits |
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HI-8110SM-32 Datasheet(HTML) 2 Page - Holt Integrated Circuits |
2 / 9 page FUNCTIONAL DESCRIPTION Whenever a Logic "0" is applied to the Chip Select ( ) input, one bit of data is clocked into the shift register from the serial data input (DIN) with each negative transition of the Clock ( ) input. is internally tied to VSS on some versions. A Logic "1" present at the Load (LD) input will cause a parallel transfer of data from the shift register to the data latch. If the Load (LD) input is held high while data is clocked into the shift register, the latch will be transparent. To display segments, a Logic "1" is stored in the appropriate shift register bit position, and the segment output is out-of- phase with the backplane. The backplane output functions in 1 of 2 modes; externally driven or self-oscillating. When the LCDØ input is externally driven with the LCDØOPT input open circuit (Figure 2), the backplane output will be in-phase with LCDØ. Utilizing the self-oscillating mode, inputs LCDØ and LCDØOPT are tied together and connected to an RC circuit (Figure 3). A 150K resistor with a 470pF capacitor generates an approximate backplane frequency of 100Hz. The LCDØ/LCDØOPT oscillator frequency is divided by 256 to determine the backplane output frequency. The resistor value (R) must be at least 30K for proper self-oscillator operation. For displays having a number of segments greater than 38, two or more of the display drivers may be cascaded together by connecting the serial data output (DOUT) from the first driver, to the serial data input (DIN) of the following driver, etc. (See Figures 2 & 3). Data out (DOUT) will change state CS CL CS All four logic inputs are TTL compatible on the HI-8010 and CMOS compatible on the HI-8110. W W HI-8010/HI-8110 Series INTERNAL OSCILLATOR CIRCUIT TO BACKPLANE TRANSLATOR AND DRIVER ÷ 256 C R LCDØ OPT LCDØ Figure 1 Q on the rising edge of the Clock ( ). Clock ( ), Load (LD) and Chip Select ( ) should be tied in common with each other, respectively, between all cascaded display drivers. CL CL CS HOLT INTEGRATED CIRCUITS 2 SYMBOL FUNCTION DESCRIPTION VSS POWER 0 Volts INPUT Logic input Chip select INPUT Logic input Clocks shift register on negative edge and DOUT pins on positive edge LD INPUT Logic input Segment outputs equal shift register data if Load is high DIN INPUT Logic input Shift register data input LCD0 INPUT Analog input Display clock input and is always bonded out. Can swing from VEE to VDD LCD0OPT OUTPUT Analog output Bonded out only if an RC oscillator is required VDD POWER 5 Volts VEE POWER 0 Volts to -30 Volts DOUT OUTPUT Logic output Selected pinout can provide shift register taps at positions 30, 32, 34, or 38 BP OUTPUT Display drive output Low resistance drive for the backplane and swings from VDD to VEE Segments OUTPUT Display drive output High resistance drive for each segment and swings from VDD to VEE CS CL PIN DESCRIPTIONS |
Similar Part No. - HI-8110SM-32 |
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Similar Description - HI-8110SM-32 |
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