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HI-3582PQT Datasheet(PDF) 5 Page - Holt Integrated Circuits |
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HI-3582PQT Datasheet(HTML) 5 Page - Holt Integrated Circuits |
5 / 16 page FIFO LOAD CONTROL SEL EN CONTROL BIT / R/W CONTROL 32 TO 16 DRIVER 32 BIT SHIFT REGISTER TO PINS CONTROLBITS CR0, CR14 CLOCK OPTION CLOCK CLK BIT COUNTER AND END OF SEQUENCE PARITY CHECK 32ND BIT DATA BIT CLOCK WORD GAP WORD GAP TIMER BIT CLOCK END START SEQUENCE CONTROL ERROR CLOCK ERROR DETECTION SHIFT REGISTER SHIFT REGISTER NULL ZEROS SHIFT REGISTER ONES EOS FIGURE 2. RECEIVER BLOCK DIAGRAM LABEL / DECODE COMPARE 16x8 LABEL MEMORY 32X32 FIFO D/R FF MUX CONTROL CONTROL BITS HF 0 X 0 X Load FIFO 1 No 0 X Ignore data 1 Yes 0 X Load FIFO 0 X 1 No Ignore data 0 X 1 Yes Load FIFO 1 Yes 1 No Ignore data 1 No 1 Yes Ignore data 1 No 1 No Ignore data 1 Yes 1 Yes Load FIFO CR2(3) ARINC word CR6(9) ARINC word FIFO matches bits 9,10 label match CR7,8 (10,11) FUNCTIONAL DESCRIPTION (cont.) RECEIVER PARITY The receiver parity circuit counts Ones received, including the parity bit. If the result is odd, then a "0" will appear in the 32nd bit. RETRIEVING DATA Once 32 valid bits are recognized, the receiver logic generates an End of Sequence (EOS). Depending upon the state of control register bits CR2-CR11, the received ARINC 32-bit word is then checked for correct decoding and label matching before being loaded into the 32 x 32 receive FIFO. ARINC words which do not meet the necessary 9th and 10th ARINC bit or label matching are ignored and are not loaded into the receive FIFO. The following table describes this operation. HI-3582, HI-3583 HOLT INTEGRATED CIRCUITS 5 |
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