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HI-6110PCI Datasheet(PDF) 4 Page - Holt Integrated Circuits |
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HI-6110PCI Datasheet(HTML) 4 Page - Holt Integrated Circuits |
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4 / 36 page  HOLT INTEGRATED CIRCUITS 4 VALMESS ERROR RCVA RCVB RF0 RF1 CLK MR BCSTART BCMODE RTMODE RFLAG Transceiver Transceiver Bus A BUSA BUSA Message Status Protocol Control Command Word 1 Manchester Encoder BUSB BUSB Control Register Status Register BC Protocol Engine Bus B Parallel to Serial Manchester Decoder Serial to Parallel Manchester Decoder Serial to Parallel Host Data Interface Command Word 2 TX DATA FIFO Status Word 1 Status Word 2 RX DATA FIFO BC Error Register D15-D0 R/ RA2-RA0 FFEMPTY CS W STR Bus A Word Bus B Word TXINHA TXINHB Mux Figure 1. Block Diagram - Bus Controller Mode INITIALIZATION In Bus Controller mode, the user must first perform a Master Reset to initialize the BC protocol engine and clear all message registers and data FIFOs. This may be achieved by pulsing the MR input high, or writing a "1" to Control Register bit 0. The user must select a master clock (CLK) frequency by programming Control Register bits 11 and 12, and the Response Time Out must be programmed per Control Register bit 14. Refer to the BC Register Formats section for a full description of available registers and their functions in Bus Controller Mode. BUS CONTROLLER The HI-6110 is configured for Bus Controller operation by setting the BCMODE input high and the RTMODE input low. Alternatively, Control Register bits 3:2 (RTMODE:BCMODE) may be programmed to 0:1. Control Register bits 3:2 are logically ORed with the input pins with the same signal name. Figure 1. shows a block diagram of the HI-6110 in Bus Controller mode HI-6110 (BUS CONTROLLER MODE) |
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Similar Description - HI-6110PCI |
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