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HI5812JIPZ Datasheet(PDF) 3 Page - Intersil Corporation |
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HI5812JIPZ Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 16 page 3 Absolute Maximum Ratings Thermal Information Supply Voltage VDD to VSS . . . . . . . . . . . . . . . . . . . . (VSS -0.5V) < VDD < +6.5V VAA+ to VAA- . . . . . . . . . . . . . . . . . . . (VSS -0.5V) to (VSS +6.5V) VAA+ to VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.3V Analog and Reference Inputs VIN, VREF+, VREF- . . . . . . . . (VSS -0.3V) < VINA < (VDD +0.3V) Digital I/O Pins . . . . . . . . . . . . . . . (VSS -0.3V) < VI/O < (VDD +0.3V) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC Thermal Resistance (Typical, Note 1) θJA (oC/W) PDIP Package*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65οC to 150oC Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications VDD = VAA+ = 5V, VREF+ = +4.608V, VSS = VAA- = VREF- = GND, CLK = External 750kHz, Unless Otherwise Specified PARAMETER TEST CONDITIONS 25oC -40oC TO 85oC UNITS MIN TYP MAX MIN MAX ACCURACY Resolution 12 - - 12 - Bits Integral Linearity Error, INL (End Point) J- - ±1.5 - ±1.5 LSB K- - ±1.0 - ±1.0 LSB Differential Linearity Error, DNL J - - ±2.0 - ±2.0 LSB K- - ±1.0 - ±1.0 LSB Gain Error, FSE (Adjustable to Zero) J- - ±3.0 - ±3.0 LSB K- - ±2.5 - ±2.5 LSB Offset Error, VOS (Adjustable to Zero) J- - ±2.0 - ±2.0 LSB K- - ±1.0 - ±1.0 LSB Power Supply Rejection, PSRR Offset Error PSRR Gain Error PSRR VREF = 4V VDD = VAA+ = 5V ±5% VDD = VAA+ = 5V ±5% - ±0.1 ±0.1 ±0.5 ±0.5 - ±0.5 ±0.5 LSB LSB DYNAMIC CHARACTERISTICS Signal to Noise Ratio, SINAD RMS Signal RMS Noise + Distortion JfS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz - 68.8 69.2 -- - dB dB KfS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz - 71.0 71.5 -- - dB dB Signal to Noise Ratio, SNR RMS Signal RMS Noise JfS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz - 70.5 71.1 -- - dB dB KfS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz - 71.5 72.1 -- - dB dB Total Harmonic Distortion, THD J fS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz - -73.9 -73.8 -- - dBc dBc KfS = Internal Clock, fIN = 1kHz fS = 750kHz, fIN = 1kHz - -80.3 -79.0 -- - dBc dBc HI5812 |
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