HI3-0516-5Z datasheet(4/8 Pages) INTERSIL

Part #	HI3-0516-5Z

Description	16-Channel/Differential 8-Channel, CMOS High Speed Analog Multiplexer

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Manufacturer	INTERSIL [Intersil Corporation]

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4

Absolute Maximum Ratings

Thermal Information

V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V

Analog Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (VIN, VOUT)

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V

Digital Input Voltage:

TTL Levels Selected (VDD/LLS Pin = GND or Open)

VA0-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +6V

VA3/SDS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . (V-) -2V to (V+) +2V

CMOS Levels Selected (VDD/LLS Pin = VDD)

VA0-3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2V to (V+) +2V

Operating Conditions

Temperature Ranges

HI-516-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC

Thermal Resistance (Typical, Note 2)

θJA (oC/W)

PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . .

60

Maximum Junction Temperature

Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

*Pb-free PDIPs can be used for through hole wave solder processing

only. They are not intended for use in Reflow solder processing

applications.

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

2.

θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications

Supplies = +15V, -15V; VAH (Logic Level High) = 2.4V, VAL (Logic Level Low) = 0.8V;

VDD/LLS = GND. (Note 3) Unless Otherwise Specified

PARAMETER

TEST

CONDITIONS

TEMP

(oC)

-5

UNITS

MIN

TYP

MAX

DYNAMIC CHARACTERISTICS

Access Time, tA

25

-

130

175

ns

Full

-

225

ns

Break-Before-Make Delay, tOPEN

25

10

20

-

ns

Enable Delay (ON), tON(EN)

25

-

120

175

ns

Enable Delay (OFF), tOFF(EN)

25

-

140

175

ns

Settling Time

To 0.1%

25

-

250

-

ns

To 0.01%

25

-

800

-

ns

Charge Injection Error

Note 6

25

-

20

mV

Off Isolation

Note 7

25

55

-

dB

Channel Input Capacitance, CS(OFF)

25

-

10

pF

Channel Output Capacitance,

CD(OFF)

25

-

25

pF

Digital Input Capacitance, CA

25

-

10

pF

Input to Output Capacitance,

CDS(OFF)

25

-

0.02

-

pF

DIGITAL INPUT CHARACTERISTICS

Input Low Threshold, VAL (TTL)

Note 3

Full

-

0.8

V

Input High Threshold, VAH (TTL)

Note 3

Full

2.4

-

V

Input Low Threshold, VAL (CMOS)

Note 3

Full

-

0.3VDD

V

Input High Threshold, VAH (CMOS)

Note 3

Full

0.7VDD

--

V

Input Leakage Current, IAH (High)

Full

-

1

µA

HI-516

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