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ADSP-BF549 Datasheet(PDF) 10 Page - Analog Devices |
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ADSP-BF549 Datasheet(HTML) 10 Page - Analog Devices |
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10 / 68 page  Rev. PrE | Page 10 of 68 | April 2007 ADSP-BF542/4/8/9 Preliminary Technical Data This register is updated automatically by the controller, but it may be written only when its corresponding IMASK bit is cleared. • CEC interrupt mask register (IMASK). The IMASK regis- ter controls the masking and unmasking of individual events. When a bit is set in the IMASK register, that event is unmasked and is processed by the CEC when asserted. A cleared bit in the IMASK register masks the event, prevent- ing the processor from servicing the event even though the event may be latched in the ILAT register. This register may be read or written while in supervisor mode. (Note that general-purpose interrupts can be globally enabled and disabled with the STI and CLI instructions, respectively.) • CEC interrupt pending register (IPEND). The IPEND reg- ister keeps track of all nested events. A set bit in the IPEND register indicates the event is currently active or nested at some level. This register is updated automatically by the controller but may be read while in supervisor mode. The SIC allows further control of event processing by providing three 32-bit interrupt control and status registers. Each register contains a bit corresponding to each of the peripheral interrupt events shown in Table 4 on Page 8. • SIC interrupt mask register (SIC_IMASK). This register controls the masking and unmasking of each peripheral interrupt event. When a bit is set in the register, that peripheral event is unmasked and is processed by the sys- tem when asserted. A cleared bit in the register masks the peripheral event, preventing the processor from servicing the event. • SIC interrupt status register (SIC_ISR). As multiple periph- erals can be mapped to a single event, this register allows the software to determine which peripheral event source triggered the interrupt. A set bit indicates the peripheral is asserting the interrupt, and a cleared bit indicates the peripheral is not asserting the event. • SIC interrupt wakeup enable register (SIC_IWR). By enabling the corresponding bit in this register, a peripheral can be configured to wake up the processor, should the core be idled when the event is generated. (For more infor- mation, see Dynamic Power Management on Page 16.) Because multiple interrupt sources can map to a single general- purpose interrupt, multiple pulse assertions can occur simulta- neously, before or during interrupt processing for an interrupt event already detected on this interrupt input. The IPEND reg- ister contents are monitored by the SIC as the interrupt acknowledgement. The appropriate ILAT register bit is set when an interrupt rising edge is detected (detection requires two core clock cycles). The bit is cleared when the respective IPEND register bit is set. The IPEND bit indicates that the event has entered into the proces- sor pipeline. At this point the CEC recognizes and queues the next rising edge event on the corresponding event input. The minimum latency from the rising edge transition of the general- purpose interrupt to the IPEND output asserted is three core clock cycles; however, the latency can be much higher, depend- ing on the activity within and the state of the processor. DMA CONTROLLERS ADSP-BF542/4/8/9 processors have multiple, independent DMA channels that support automated data transfers with min- imal overhead for the processor core. DMA transfers can occur between the ADSP-BF542/4/8/9 processor’s internal memories and any of its DMA-capable peripherals. Additionally, DMA transfers can be accomplished between any of the DMA-capable peripherals and external devices connected to the external memory interfaces, including DDR and asynchronous memory controllers. While the USB controller and MXVR have their own dedicated DMA controllers, the other on-chip peripherals are managed by two centralized DMA controllers, called DMAC1 (32-bit) and DMAC0 (16-bit). Both operate in the SCLK domain. Each DMA controller manages twelve independent DMA channels. The DMAC1 controller masters high-bandwidth peripherals over a dedicated 32-bit DMA access bus (DAB32). Similarly, the DMAC0 controller masters most of serial interfaces over the 16- bit DAB16 bus. Individual DMA channels have fixed access pri- ority on the DAB buses. DMA priority of peripherals is managed by flexible peripheral-to-DMA channel assignment. All four DMA controllers use the same 32-bit DCB bus to exchange data with L1 memory. This includes L1 ROM, but excludes scratchpad memory. Fine granulation of L1 memory and special DMA buffers minimize potential memory conflicts, if the L1 memory is accessed by the core contemporaneously. Similarly, there are dedicated DMA buses between the DMAC1, DMAC0, and USB DMA controllers and the external bus inter- face unit (EBIU) that arbitrates DMA accesses to external memories and boot ROM. The ADSP-BF542/4/8/9 processor DMA controllers support both 1-dimensional (1D) and 2-dimensional (2D) DMA trans- fers. DMA transfer initialization can be implemented from registers or from sets of parameters called descriptor blocks. The 2D DMA capability supports arbitrary row and column sizes up to 64K elements by 64K elements, and arbitrary row and column step sizes up to ±32K elements. Furthermore, the column step size can be less than the row step size, allowing implementation of interleaved data streams. This feature is especially useful in video applications where data can be de- interleaved on the fly. Examples of DMA types supported by the ADSP-BF542/4/8/9 processor DMA controller include: • A single, linear buffer that stops upon completion • A circular, auto-refreshing buffer that interrupts on each full or fractionally full buffer • 1-D or 2-D DMA using a linked list of descriptors • 2-D DMA using an array of descriptors, specifying only the base DMA address within a common page In addition to the dedicated peripheral DMA channels, both the DMAC1 and the DMAC0 controllers feature two memory DMA channel pairs for transfers between the various memories of the ADSP-BF542/4/8/9 processor system. This enables trans- fers of blocks of data between any of the memories—including |
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