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| USB97C102 |
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 SMSC
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5 page 
SMSC DS – USB97C102 Page 5 Rev. 03/23/2000 DESCRIPTION OF PIN FUNCTIONS Table 1 - USB97C102 Pin Configuration QFP PIN NUMBER SYMBOL PIN DESCRIPTION BUFFER TYPE ISA INTERFACE 100 READY Channel is ready when high. ISA memory or slave devices use this signal to lengthen a bus cycle from the default time. Extending the length of the bus cycle can only be done when the bus cycles are derived from the Internal DMA controller core. 8051 MCU generated Memory or I/O accesses cannot and will not be extended even if READY is asserted low by an external ISA slave device. The external slave device negates this signal after decoding a valid address and sampling the command signals (nIOW, nIOR, nMEMW, and nMEMR). When the slave’s access has completed, this signal should be allowed to float high. IP 104, 106, 108, 110 DRQ[3:0] DMA Request channels 3-0; active high. These signals are used to request DMA service from the DMA controller. The requesting device must hold the request signal until the DMA controller drives the appropriate DMA acknowledge signal (nDACK[3:0]). I 105, 107, 109, 111 nDACK [3:0] DMA Acknowledge channels 3-0; active low. These signals are used to indicate to the DMA requesting device that it has been granted the ISA bus. O8 103 TC DMA Terminal Count; active high. This signal is used to indicate that a DMA transfer has completed. O8 19-13, 127-7, 9-12 SA[19:0] System Address Bus These signals address memory or I/O devices on the ISA bus. O8 112-115, 117- 120 SD[7:0] System Data Bus These signals are used to transfer data between system devices. I/O8 122 AEN Address Enable This signal indicates address validation to I/O devices. When low this signal indicates that an I/O slave may respond to addresses and I/O commands on the bus. This signal is high during DMA cycles to prevent I/O slaves from interpreting DMA cycles as valid I/O cycles. O8 123 nIOW I/O Write; active low. This signal indicates to the addressed ISA I/O slave to latch data from the ISA bus. O8 124 nIOR I/O Read; active low. This signal indicates to the addressed ISA I/O slave to drive data on the ISA bus. O8 125 nMEMR Memory read; active low This signal indicates to the addressed ISA memory slave to drive data on the ISA bus. O8 126 nMEMW Memory write; active low This signal indicates to the addressed ISA memory slave to latch data from the ISA bus. O8 102 nMASTER External Bus master, active low This signal forces the USB97C102 to immediately tri-state its external bus, even if internal transactions are not complete. All shared ISA signals are tri-stated, except 8237 nDACKs, which can be used in gang mode to provide external bus-master handshaking. This pin must be used with some handshake mechanism to avoid data corruption. IP 21-24 IRQ[3:0] Interrupt Request 3-0; active high These signals are driven by ISA devices on the ISA bus to interrupt the 8051. I |
