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IRF540 Datasheet(PDF) 2 Page - NXP Semiconductors |
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IRF540 Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 9 page Philips Semiconductors Product specification N-channel TrenchMOS ™ transistor IRF540, IRF540S AVALANCHE ENERGY LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT E AS Non-repetitive avalanche Unclamped inductive load, I AS = 10 A; - 230 mJ energy t p = 350 µs; Tj prior to avalanche = 25˚C; V DD ≤ 25 V; RGS = 50 Ω; VGS = 10 V; refer to fig:14 I AS Peak non-repetitive - 23 A avalanche current THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT R th j-mb Thermal resistance junction - - 1.5 K/W to mounting base R th j-a Thermal resistance junction SOT78 package, in free air - 60 - K/W to ambient SOT404 package, pcb mounted, minimum - 50 - K/W footprint ELECTRICAL CHARACTERISTICS T j= 25˚C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V (BR)DSS Drain-source breakdown V GS = 0 V; ID = 0.25 mA; 100 - - V voltage T j = -55˚C 89 - - V V GS(TO) Gate threshold voltage V DS = VGS; ID = 1 mA 2 3 4 V T j = 175˚C 1 - - V T j = -55˚C - - 6 V R DS(ON) Drain-source on-state V GS = 10 V; ID = 17 A - 49 77 m Ω resistance T j = 175˚C - 132 193 m Ω g fs Forward transconductance V DS = 25 V; ID = 17 A 8.7 15.5 - S I GSS Gate source leakage current V GS = ± 20 V; VDS = 0 V - 10 100 nA I DSS Zero gate voltage drain V DS = 100 V; VGS = 0 V - 0.05 10 µA current V DS = 80 V; VGS = 0 V; Tj = 175˚C - - 250 µA Q g(tot) Total gate charge I D = 17 A; VDD = 80 V; VGS = 10 V - - 65 nC Q gs Gate-source charge - - 10 nC Q gd Gate-drain (Miller) charge - - 29 nC t d on Turn-on delay time V DD = 50 V; RD = 2.2 Ω;- 8 - ns t r Turn-on rise time V GS = 10 V; RG = 5.6 Ω -39 - ns t d off Turn-off delay time Resistive load - 26 - ns t f Turn-off fall time - 24 - ns L d Internal drain inductance Measured tab to centre of die - 3.5 - nH L d Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH (SOT78 package only) L s Internal source inductance Measured from source lead to source - 7.5 - nH bond pad C iss Input capacitance V GS = 0 V; VDS = 25 V; f = 1 MHz - 890 1187 pF C oss Output capacitance - 139 167 pF C rss Feedback capacitance - 83 109 pF August 1999 2 Rev 1.100 |
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