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CP80C86-2 Datasheet(PDF) 9 Page - Intersil Corporation |
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CP80C86-2 Datasheet(HTML) 9 Page - Intersil Corporation |
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9 / 37 page  149 Status bits S3 through S7 are time multiplexed with high order address bits and the BHE signal, and are therefore valid during T2 through T4. S3 and S4 indicate which seg- ment register (see Instruction Set Description) was used for this bus cycle in forming the address, according to Table 3. S5 is a reflection of the PSW interrupt enable bit. S3 is always zero and S7 is a spare status bit. I/O Addressing In the 80C86, I/O operations can address up to a maximum of 64K I/O byte registers or 32K I/O word registers. The I/O address appears in the same format as the memory address on bus lines A15-A0. The address lines A19-A16 are zero in I/O operations. The variable I/O instructions which use regis- ter DX as a pointer have full address capability while the direct I/O instructions directly address one or two of the 256 I/O byte locations in page 0 of the I/O address space. I/O ports are addressed in the same manner as memory loca- tions. Even addressed bytes are transferred on the D7-D0 bus lines and odd addressed bytes on D15-D8. Care must be taken to ensure that each register within an 8-bit peripheral located on the lower portion of the bus be addressed as even. TABLE 3. S4 S3 CHARACTERISTICS 0 0 Alternate Data (Extra Segment) 01 Stack 1 0 Code or None 11 Data TYPE 225 POINTER (AVAILABLE) RESET BOOTSTRAP PROGRAM JUMP TYPE 33 POINTER (AVAILABLE) TYPE 32 POINTER (AVAILABLE) TYPE 31 POINTER (AVAILABLE) TYPE 5 POINTER (RESERVED) TYPE 4 POINTER OVERFLOW TYPE 3 POINTER 1 BYTE INT INSTRUCTION TYPE 2 POINTER NON MASKABLE TYPE 1 POINTER SINGLE STEP TYPE 0 POINTER DIVIDE ERROR 16 BITS CS BASE ADDRESS IP OFFSET 014H 010H 00CH 008H 004H 000H 07FH 080H 084H FFFF0H FFFFFH 3FFH 3FCH AVAILABLE INTERRUPT POINTERS (224) DEDICATED INTERRUPT POINTERS (5) RESERVED INTERRUPT POINTERS (27) FIGURE 2. RESERVED MEMORY LOCATIONS 80C86 |
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