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BLOCK DIAGRAM

LNAI

Mixer

Dual Stage-LNA

LO Buffer

VGA

LOP

VDD1

RFAGC

LON

BALUN

LNAO MXRI

IFOP

IFON

RFATTN

VDDLO

IFB

VDDIF

VDD2

GND

B0084-01

TRF1216

SLWS172A – APRIL 2005 – REVISED DECEMBER 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the device

placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

The detailed block diagram and the pin-out of the ASIC are shown in Figure 1 and Table 1.

Figure 1. Detailed Block Diagram of TRF1216

TERMINAL FUNCTIONS

TERMINAL

I/O

TYPE

DESCRIPTION

NO.

NAME

1

LNAO

O

Analog

LNA Output, 50

Ω, ac-coupled

2

VDD1

I

Power

LNA1 DC Bias (+5 V nominal)

3, 4, 6, 9,

GND

–

–

Ground

16, 19

5

LNAI

I

Analog

RF input – Needs dc block and input matching for optimum noise figure

7

LOP

I

Analog

LO input positive, ac coupled

8

LON

I

Analog

LO input negative, ac coupled

10

VDDLO

I

Power

LO DC Bias (+5 V nominal)

Not connected for normal operation. IF Bias Adjustment. Do not ground this pin or connect to any

11

IFB

–

–

other pin.

12

VDDIF

I

Power

IF Bias Network dc Bias (+5 V nominal)

13

IFON

O

Analog

IF output and bias (see the application schematic for connections).

14

IFOP

O

Analog

IF output and bias (see the application schematic for connections).

15

RFAGC

I

Analog

TTL control for switched attenuator TTL low – Attenuator switched in TTL high – Attenuator

17

RFATTN

I

Digital

switched out

18

MXRI

I

Analog

Mixer Input 50

Ω

20

VDD2

–

Power

LNA2 dc bias (+5 V nominal)

Back

GND

–

–

Back of package has metal base that must be grounded for thermal and RF performance.

2