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TRF1223 Datasheet(PDF) 3 Page - Texas Instruments |
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TRF1223 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 13 page www.ti.com SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS TRF1223 SLWS166C – APRIL 2005 – REVISED MARCH 2007 Table 1. Pin Out of TRF1223 (continued) PIN # PIN NAME I/O TYPE DESCRIPTION 8 PAGAIN0 I Digital First 16-dB attenuator gain control. Logic high is high gain and logic low is low gain. 9 PAGAIN1 I Digital Second 16-dB gain control. Logic high is high gain and logic low is low gain. 10 VADJ2 I Analog No connection required for normal operation. May be used to adjust FET2 bias. DO NOT GROUND THIS PIN OR CONNECT TO ANY OTHER PIN. 11-14 GND - - Ground 15 VADJ3 I Analog No connection required for normal operation. May be used to adjust FET3 bias DO NOT GROUND THIS PIN OR CONNECT TO ANY OTHER PIN. 16 LP I Digital Low power mode: Active high. Low power mode is lower dc and POUT mode. 17 PACNT I Digital Power amplifier enable, High is PA on, logic low is PA off (low current) 18 VDD3B I Power Stage 3 dc-drain supply power. This pin is internally dc connected to pin 23 (VDD3A). Bias must be provided to both pins for optimal performance. The total dc-current through these two pins is typically 70% of IDD. 19 GND - - Ground 20 RFO O Analog RF output, internal dc block 21 RFO O Analog RF output, internal dc block 22 GND - - Ground 23 VDD3A I Power Stage 3 dc-rain supply power. This pin is internally dc connected to pin 18 (VDD3B). Bias must be provided to both pins for optimal performance. The total dc-current through these two pins is typically 70% of IDD. 24 DETP O Analog Detector output, positive. Voltage will be 0.5 V with/without RF output 25 DETN O Analog Detector output, negative. Voltage is 0.5 V with no RF and decreases with increasing RF output power. 26-31 GND - - Ground 32 VDD2 I Power Stage 2 dc-drain supply power. The dc current through this pin is typically 25% of IDD. Back - - Back of package has a metal base which must be grounded for thermal and RF performance. PARAMETER TEST CONDITION MIN MAX UNIT VDD 0 8 V VPOS DC supply voltage 0 5.5 V VNEG -5.5 0 V I DD Current consumption 1300 mA Pin RF input power 20 dBm Tj Junction temperature 175 °C Pd Power dissipation 6.5 W Digital input pins -0.3 5.5 Θ jc Thermal resistance junction to 20 °C/W case(1) Tstg Storage temperature -40 105 °C Top Operating temperature Maximum case temperature derate for -40 85 °C PCB thermal resistance Lead temperature 40 sec maximum 220 °C (1) Thermal resistance is junction to case assuming thermal pad with 25 thermal vias under package metal base. See the recommended layout Figure 6 and application note RA1005 for more detail. 3 Submit Documentation Feedback |
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