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CA3140 Datasheet(PDF) 8 Page - Intersil Corporation |
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CA3140 Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 23 page 8 FN957.10 July 11, 2005 Bandwidth and Slew Rate For those cases where bandwidth reduction is desired, for example, broadband noise reduction, an external capacitor connected between Terminals 1 and 8 can reduce the open loop -3dB bandwidth. The slew rate will, however, also be proportionally reduced by using this additional capacitor. Thus, a 20% reduction in bandwidth by this technique will also reduce the slew rate by about 20%. Figure 5 shows the typical settling time required to reach 1mV or 10mV of the final value for various levels of large signal inputs for the voltage follower and inverting unity gain amplifiers. The exceptionally fast settling time characteristics are largely due to the high combination of high gain and wide bandwidth of the CA3140; as shown in Figure 6. Input Circuit Considerations As mentioned previously, the amplifier inputs can be driven below the Terminal 4 potential, but a series current limiting resistor is recommended to limit the maximum input terminal current to less than 1mA to prevent damage to the input protection circuitry. Moreover, some current limiting resistance should be provided between the inverting input and the output when FIGURE 4. METHODS OF UTILIZING THE VCE(SAT) SINKING CURRENT CAPABILITY OF THE CA3140 SERIES 3 2 4 CA3140 7 6 LOAD RL RS MT2 MT1 30V NO LOAD 120VAC 3 2 4 CA3140 7 6 V+ +HV LOAD RL FIGURE 5A. WAVEFORM FIGURE 5B. TEST CIRCUITS FIGURE 5. SETTLING TIME vs INPUT VOLTAGE SETTLING TIME ( µs) 0.1 1.0 10 SUPPLY VOLTAGE: VS = ±15V TA = 25 oC 1mV 10mV 10mV 1mV 1mV 1mV 10mV FOLLOWER INVERTING LOAD RESISTANCE (RL) = 2kΩ LOAD CAPACITANCE (CL) = 100pF 10 8 6 4 2 0 -2 -4 -6 -8 -10 10mV 3 2 CA3140 6 SIMULATED LOAD 4 -15V 0.1 µF 5.11k Ω 0.1 µF 7 +15V 5k Ω 2k Ω 100pF 5k Ω INVERTING SETTLING POINT 200 Ω 4.99k Ω D1 1N914 D2 1N914 2 CA3140 6 SIMULATED LOAD 4 -15V 0.1 µF 0.1 µF 7 +15V 2k Ω 100pF 0.05 µF 2k Ω 3 10k Ω FOLLOWER CA3140, CA3140A |
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