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HEF40194B Datasheet(PDF) 2 Page - NXP Semiconductors |
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HEF40194B Datasheet(HTML) 2 Page - NXP Semiconductors |
2 / 8 page January 1995 2 Philips Semiconductors Product specification 4-bit bidirectional universal shift register HEF40194B MSI DESCRIPTION The HEF40194B is a 4-bit bidirectional shift register with two mode control inputs (S0 and S1), a clock input (CP), a serial data shift left input (DSL), a serial data shift right input (DSR), four parallel data inputs (P0 to P3), an overriding asynchronous master reset input (MR), and four buffered parallel outputs (O0 to O3). When LOW, MR resets all stages and forces O0 to O3 LOW, overriding all other input conditions. When MR is HIGH, the operation mode is controlled by S0 and S1 as shown in the function table. Serial and parallel operation are edge-triggered on the LOW to HIGH transition of CP. The inputs at which the data are to be entered and S0, S1 must be stable for a set-up time before the LOW to HIGH transition of CP. Fig.1 Functional diagram. HEF40194BP(N): 16-lead DIL; plastic (SOT38-1) HEF40194BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF40194BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America Fig.2 Pinning diagram. PINNING S0, S1 mode control inputs P0 to P3 parallel data inputs DSR serial data shift right input DSL serial data shift left input CP clock input (LOW to HIGH edge-triggered) MR master reset input (active LOW) O0 to O3 buffered parallel outputs FAMILY DATA, IDD LIMITS category MSI See Family Specifications |
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