January 1995

2

Philips Semiconductors

Product specification

4-bit synchronous decade counter with

synchronous reset

HEF40162B

MSI

DESCRIPTION

The HEF40162B is a fully synchronous edge-triggered

4-bit decade counter with a clock input (CP), four

synchronous mode control inputs (parallel enable (PE),

count enable parallel (CEP), count enable trickle (CET)

and synchronous reset (SR)), buffered outputs from all

(TC).

Operation is synchronous and occurs on the LOW to HIGH

transition of CP. When PE is LOW, the next LOW to HIGH

When PE is HIGH, the next LOW to HIGH transition of CP

advances the counter to its next state only if both CEP and

CET are HIGH; otherwise no change occurs in the state of

the counter. TC is HIGH when the state of the counter is 9

LOW on the next LOW to HIGH transition of CP,

independent of the state of all other synchronous mode

control inputs (CEP, CET and PE). Multistage

synchronous counting is possible without additional

components by using a carry look-ahead counting

technique; in this case, TC is used to enable successive

cascaded stages. CEP, CET, PE and SR must be stable

only during the set-up time before the LOW to HIGH

transition of CP.

See Family Specifications

Fig.1 Functional diagram.