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HEF4000BF Datasheet(PDF) 3 Page - NXP Semiconductors |
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HEF4000BF Datasheet(HTML) 3 Page - NXP Semiconductors |
3 / 5 page January 1995 3 Philips Semiconductors Product specification Dual 3-input NOR gate and inverter HEF4000B gates DC CHARACTERISTICS For the single inverter stage (I7/O3): see Family Specifications for input voltages HIGH and LOW (unbuffered stages only). AC CHARACTERISTICS VSS = 0 V; Tamb =25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V SYMBOL TYP. MAX. TYPICAL EXTRAPOLATION FORMULA Propagation delays 5 70 140 ns 43 ns + (0,55 ns/pF) CL I1 to I6 → O1,O2 10 tPHL; tPLH 35 70 ns 24 ns + (0,23 ns/pF) CL 15 30 55 ns 22 ns + (0,16 ns/pF) CL 5 45 90 ns 18 ns + (0,55 ns/pF) CL I7 → O3 10 tPHL; tPLH 25 50 ns 14 ns + (0,23 ns/pF) CL (unbuffered output) 15 20 40 ns 12 ns + (0,16 ns/pF) CL Output transition times 5 60 120 ns 10 ns + (1,0 ns/pF) CL HIGH to LOW 10 tTHL 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL 5 60 120 ns 10 ns + (1,0 ns/pF) CL LOW to HIGH 10 tTLH 30 60 ns 9 ns + (0,42 ns/pF) CL 15 20 40 ns 6 ns + (0,28 ns/pF) CL VDD V TYPICAL FORMULA FOR P ( µW) Dynamic power 5 1 000 fi +∑ (foCL) × VDD2 where dissipation per 10 7 700 fi +∑ (foCL) × VDD2 fi = input freq. (MHz) package (P) 15 28 700 fi +∑ (foCL) × VDD2 fo = output freq. (MHz) CL = load capacitance (pF) ∑ (f oCL) = sum of outputs VDD = supply voltage (V) |
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