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FAN5033 Datasheet(PDF) 4 Page - Fairchild Semiconductor |
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FAN5033 Datasheet(HTML) 4 Page - Fairchild Semiconductor |
4 / 39 page © 2006 Fairchild Semiconductor 2006 www.fairchildsemi.com FAN5033 Rev. 1.0.0 4 of 39 Pin # Name Description 14 GND Ground. All internal biasing and logic output signals of the device are referenced to this ground. 15 OD Output Disable. This pin is actively pulled low when the EN input is low or when VCC is below its UVLO threshold to disable the external MOSFET drivers. (Also referred to as OD# in the text of this document.) 16 NC No Connection. This pin is not connected internally. 17 to 19 SW3 to SW1 Switching Node Current Balance Inputs. Sense the switching side of the inductor and used to measure the current level in each phase. The SW pins of unused phases should be left open. 20 to 22 PWM3 to PWM1 PWM Outputs. Each output is connected to the input of an external MOSFET driver, such as the FAN5109. Connecting the PWM3 output to VCC disables that phase, allowing the FAN5033 to operate as a two-phase controller. 23 VCC Supply Voltage for the Device. 24 to 31 VID7 to VID0 Voltage Identification Code Inputs. These digital inputs are connected to the internal DAC and used to program the output voltage. These pins have 1µA internal pull-down; so if they are left open, the input state is decoded as logic low. 32 VIDSEL VID Table Select Input. A logic low selects the extended VR10 DAC table and a logic high selects the VR11 DAC table. This pin has a 1µA internal pull-down; so if left open, the input state is decoded as logic low. - Exposed Paddle Internally connected to die ground. May be connected to ground or left floating. Connect to ground for lowest package thermal resistance. |
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