5

SY89837U

Micrel, Inc.

M9999-022007

hbwhelp@micrel.com or (408) 955-1690

Case #2 Input Clock Failure: Switching from a selected clock

stuck HIGH to a valid clock (RPE enabled).

If CLK1 fails HIGH before the RPE MUX selects CLK2

(using the SEL pin), the switchover will occur in three stages:

• Stage 1: The output will remain HIGH for a

limited number of pulses of CLK2.

• Stage 2: The output will switch to LOW and then

remain LOW for a limited number of falling edges

of CLK2.

• Stage 3: The output will follow CLK2.

Case #3 Input Clock Failure: Switching from a selected clock

stuck LOW to a valid clock (RPE enabled).

If CLK1 fails LOW before the RPE MUX selects CLK2

(using the SEL pin), the switchover will occur in two stages.

• Stage 1: The output will remain LOW for a

limited number of falling edges of CLK2.

• Stage 2: The output will follow CLK2.

CLK1

CLK2

SEL

OUTPUT

Select CLK1

Stage 1

Stage 2

Stage 3

Select CLK2

14 to 16 falling edges of CLK2

Runt pulse eliminated

from output

CLK1

CLK2

SEL

OUTPUT

Select CLK1

Stage 1

Stage 2

Select CLK2

13 to 17 falling edges of CLK2

Figure 4. Timing Diagram 3

Note:

1. Output shows extended clock cycle during switchover. Pulse width for both high and low of this cycle will always be greater than 50% of the CLK2

period.