SY89834UMGTR datasheet(2/10 Pages) MICREL

Part #	SY89834UMGTR

Description	2.5V/3.3V TWO INPUT, 1GHz LVTTL/CMOSTO-LVPECL 1:4 FANOUT BUFFER/TRANSLATOR WITH 2:1 INPUT MUX

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Manufacturer	MICREL [Micrel Semiconductor]

Direct Link	http://www.micrel.com

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2

Precision Edge®

SY89834U

Micrel, Inc.

M9999-080505

hbwhelp@micrel.com or (408) 955-1690

IN1

IN2

EN

SEL

Q0–Q3

/Q0–Q3

0

X

110

1

X

111

0

X

0100

1

X

1101

0

XX

0

X

0(1)

Note:

1. On next negative transition of the input signal (IN).

TRUTH TABLE

PACKAGE/ORDERING INFORMATION

Ordering Information(1)

Package

Operating

Package

Lead

Part Number

Type

Range

Marking

Finish

SY89834UMI

MLF-16

Industrial

834U

Sn-Pb

SY89834UMITR(2)

MLF-16

Industrial

834U

Sn-Pb

SY89834UMG(3)

MLF-16

Industrial

834U with Pb-Free

NiPdAu

bar line indicator

Pb-Free

SY89834UMGTR(2, 3)

MLF-16

Industrial

834U with Pb-Free

NiPdAu

bar line indicator

Pb-Free

Notes:

1. Contact factory for die availability. Dice are guaranteed at T

A = 25°C, DC Electricals only.

2. Tape and Reel.

3. Pb-Free package is recommended for new designs.

Pin Number

Pin Name

Pin Function

15, 16

Q0, /Q0

Differential 100K LVPECL Outputs: These LVPECL outputs are the precision, low skew copies

1, 2,

Q1, /Q1

of the inputs. Please refer to the “Truth Table” section for details. Unused output pairs may be

3, 4,

Q2, /Q2

left open. Terminate wtih 50

Ω to V

CC–2V. See “Output Termination Recommendations” section

5, 6

Q3, /Q3

for more details.

8

EN

This single-ended TTL/CMOS-compatible input functions as a synchronous output enable. The

synchronous enable ensures that enable/disable will only occur when the outputs are in a logic

LOW state. Note that this input is internally connected to a 25k

Ω pull-up resistor and will default

to logic HIGH state (enabled) if left open.

12,

IN1

Single-ended TTL/CMOS-compatible inputs to the device. These inputs are internally connected

9

IN2

to a 25k

Ω pull-up resistor and will default to logic HIGH state if left open. The input threshold is

VCC/2.

10

NC

No connect. Not internally connected.

11

SEL

TTL/CMOS Compatible Select Input for signals IN1 and IN2. The input threshold is V

CC/2. HIGH at

the SEL input selects signal IN1. LOW at the SEL input selects signal IN2. SEL includes a 25k

Ω

pull-up resistor. The default state is HIGH when left floating.

13

GND

Ground. GND pins and exposed pad must be connected to the most negative potential of the

device ground.

7, 14

VCC

Positive Power Supply: Bypass with 0.1

µF//0.01µF low ESR capacitors and place as close to

each VCC pin as possible.

PIN DESCRIPTION

13

14

15

16

12

11

10

9

1

2

3

4

8

7

6

5

Q1

/Q1

Q2

/Q2

IN1

SEL

NC

IN2

16-Pin MLF™ (MLF-16)

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