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SY89826LHI Datasheet(PDF) 5 Page - Micrel Semiconductor |
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SY89826LHI Datasheet(HTML) 5 Page - Micrel Semiconductor |
5 / 10 page 5 Precision Edge® SY89826L Micrel, Inc. M9999-011907 hbwhelp@micrel.com or (408) 955-1690 VCC = 3.3V ±10%, TA = –40°C to +85°C, unless noted. Symbol Parameter Condition Min Typ Max Units fMAX Maximum Toggle Frequency Note 2 1.0 GHz tPHL Differential Propagation Delay, LVPECL Input: 150mV 0.750 1.0 1.250 ns tPLH Note 3 LVPECL Input: 800mV 0.6 0.850 1.10 ns LVDS Input: 100mV 0.950 1.2 1.450 ns LVDS Input: 400mV 0.800 1.0 1.30 ns tSWITCHOVER Clock Input Switchover CLK_SEL-to-Valid Output 1.4 1.7 ns tS(OE) Output Enable Set-Up Time Note 4 1.0 ns tH(OE) Output Enable Hold Time Note 4 0.5 ns tskew Within Device Skew Note 5 0 °C to +85°C25 50 ps –40 °C75 ps Part-to-Part Skew Note 6 400 ps tJITTER Cycle-to-Cycle Note 7 1ps RMS Total Jitter Note 8 <1 2 ps PP tr, tf Output Rise/Fall Times 200 290 400 ps (20% to 80%) Note 1. 100 Ω termination between Q and /Q outputs. Airflow ≥300lfpm, or exposed pad soldered to ground plane. Typicals are at nominal supply, T A = 25°C. Note 2. fMAX is defined as the maximum toggle frequency, measured with a 750mV LVPECL input or 350mV LVDS input. Output swing is ≥ 200mV. Note 3. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals. Note 4. Set-up and hold time applies to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold time does not apply. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures outputs remain disabled during the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock. Note 5. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device with identical input transition, operating at the same voltage and temperature. Note 6. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. Part-to-part skew is the total skew difference; pin-to-pin skew + part-to-part skew. Note 7. Cycle-to-cycle jitter definition: The variation in period between adjacent cycles over a random sample of adjacent cycle pairs. T JITTER_CC =Tn–Tn+1 where T is the time between rising edges of the output signal. Note 8. Total jitter definition: with an ideal clock input, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to- peak jitter value. AC ELECTRICAL CHARACTERISTICS(1) |
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