5

SY89823L

Micrel, Inc.

M9999-011907

hbwhelp@micrel.com or (408) 955-1690

TIMING DIAGRAMS

CLK

OE

Q0 - Q21

Assert Latency

De-assert Latency

HSTL_CLK, LVPECL_CLK

/HSTL_CLK, /LVPECL_CLK

Q0 - Q21

/Q0 - /Q21

CLK_SEL

Q0 - Q21

/Q0 - /Q21

Notes:

1. The OE input signal must be a minimum of 3 clock periods with width.

2. The internal enable is asserted and de-asserted on the falling edge of clock.

3. The internal enable occurs 2.5 clock cycles (plus the set-up time of OE with the rising edge of clock) after the rising edge of the external OE.