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SY89536LHH Datasheet(PDF) 10 Page - Micrel Semiconductor |
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SY89536LHH Datasheet(HTML) 10 Page - Micrel Semiconductor |
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10 / 16 page  10 Precision Edge® SY89536L Micrel, Inc. M9999-110405 hbwhelp@micrel.com or (408) 955-1690 *For VCC_Analog,VCC_TTL, VCC1, use ferrite bead = 200mA, 0.45 Ω DC, Murata P/N BLM21A1025 *For VCCOA,B,C use ferrite bead = 3A, 0.025 Ω DC, Murata, P/N BLM31P005 *Component size: 0805 1 µF 22 µF 0.01 µF Ferrite Bead* Power Supply side Device side VCC Pins Figure 2. Power Supply Filtering Output Logic Characteristics See “Output Termination Recommendations” for illustrations. In cases where single-ended output is desired, the designer should terminate the unused complimentary output in the same manner as the normal output that is being used. Unused output pairs can be left floating. LVPECL operation: • Typical voltage swing is 700mV PP to 800mVPP into 50 Ω. • Common mode voltage is V CC–1.3V, typical. • 100 Ω termination across the output pair is NOT recommended for LVPECL. See “Output Termination” section, Figures 5 to 7. HSTL operation (Bank B): • Typical voltage swing is 250mV PP to 450mVPP into effective 50 Ω. Thermal Considerations This part has an exposed die pad for enhanced heat dissipation. We strongly recommend soldering the exposed die pad to a ground plane. Where this is not possible, we recommend maintaining at least 500lfpm air flow around the part. For additional information on exposed-pad characteristics and implementation details, see Amkor Technology’s web site, www.amkor.com. REFCLK Input Interface The flexible REFCLK inputs are designed to accept any differential or single-ended input signal within 300mV above VCC and 300mV below ground. Do not leave unused REFCLK inputs floating. Tie either the true or complement inputs to ground, but not both. A logic zero is achieved by connecting the complement input to ground with the true input floating. For a TTL input, tie a resistor between the complement input and ground. See “Input Interface” section, Figures 4a through 4h. Input Levels LVDS, CML and HSTL differential signals may be connected directly to the REFCLK inputs. Depending on the actual worst case voltage seen, the minimum input voltage swing varies. R2 990 Ω R2 990 Ω R1 825 Ω R1 825 Ω GND REFCLK VCC /REFCLK Figure 3. Simplified Input Structure |
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