9

SY89536L

Micrel, Inc.

M9999-110405

hbwhelp@micrel.com or (408) 955-1690

FUNCTIONAL DESCRIPTION

At the core of the SY89536L clock synthesizer is a

precision PLL driven by a differential or single-ended

reference input. For users who wish to supply a crystal

input, please use the SY89531L. The PLL output is sent to

three banks of outputs. Each bank has its own programmable

frequency divider, and the design is optimized to provide

very low skew between banks, and very low jitter.

PLL Programming and Operation

IMPORTANT: If the internal VCO will be used, VCO_SEL

must be tied LOW, and ExtVCO pins can be left

unconnected. The internal VCO range is 600MHz to

1000MHz, and the feedback ratio is selectable via the MSEL

divider control (M3:0 pins). The feedback ratio can be

changed without powering the chip down. The PLL output

is fed to three banks of outputs: Bank A, Bank B, and Bank

C. Banks A and C each have two differential LVPECL output

pairs. Bank B has nine differential HSTL output pairs.

Each bank has a separate frequency divider circuit that

can be reprogrammed on the fly. The FSEL_x0:2 (where x

is A, B, or C) pins control the divider value. The FSEL

divider can be programmed in ratios from 2 to 18, and the

outputs of Banks A, B, and C can be synchronized after

programming by pulsing the OUT_SYNC pin HIGH-LOW-

HIGH. Setting a value of 000 for FSEL is an output disable

forcing the Q outputs to be LOW and the /Q outputs to be

HIGH. Doing so will decrease power consumption by

approximately 5mA per bank.

To determine the correct settings for SY89536L follow

these steps:

1. Refer to the

“Suggested Selections for Specific

Customer Applications” section for common applications,

as well as the formula used to compute the output frequency.

2. Determine the desired output frequency, such as

66MHz.

3. Choose a reference input frequency between 14MHz

and 20MHz. The user can also choose a higher input

frequency, and use the PSEL pre-divider to divide it down

to the 14MHz to 20MHz range. In this example, we choose

18MHz for the reference input frequency. This results in an

input/output ratio of 66/18.

4. Refer to the

“Feedback Divide Select” table and the

“Post-Divide Frequency Select” table to find values for MSEL

and FSEL such that MSEL/FSEL equals the same 66/18

ratio. In this example, values of MSEL=44 and FSEL=12

work.

5. Make sure that REFCLK

÷ PSEL × MSEL is between

600MHz and 1000MHz.

The user may need to experiment with different REFCLK

input frequencies to satisfy these requirements.

470pF

Loop

Filter

Loop

Reference

330

Ω

0.2

µF

Figure 1. External Loop Filter Connection

External Loop Filter Considerations

The SY89536L features an external PLL loop filter that

allows the user to tailor the PLL’s behavior to their application

and operating environment. We recommend using ceramic

capacitors with NPO or X7R dielectric, as they have very

low effective series resistance. For applications that require

ultra-low cycle-to-cycle jitter, use the components shown in

Figure 1. The PLL loop bandwidth is a function of feedback

divider ratio, and the external loop filter allows the user to

compensate. For instance, the PLL’s loop bandwidth can

be decreased by using a smaller resistor in the loop filter.

This results in less noise from the PLL input, but potentially

more noise from the VCO. Refer to

“AC Electrical

Characteristics” for target PLL loop bandwidth. The designer

should take care to keep the loop filter components on the

same side of the board and as close as possible to the

SY89536L’s LOOP_REF and LOOP_FILTER pins. To insure

minimal noise pick-up on the loop filter, it is desirable to cut

away the ground plane directly underneath the loop filter

component pads and traces. However, the benefit may not

be significant in all applications and one must be careful to

not alter the characteristic impedance of nearby traces.

Power Supply Filtering Techniques

As with any high-speed integrated circuit, power supply

filtering is very important. At a minimum, V

and all V

via to the power supply plane, and separate bypass

capacitors should be used for each pin. To achieve optimal

jitter performance, each power supply pin should use

separate instances of the circuit shown in Figure 2.