9

SY89534/35L

Micrel, Inc.

M9999-110405

hbwhelp@micrel.com or (408) 955-1690

REFCLK Input Interface

The flexible REFCLK inputs are designed to accept any

differential to single-ended input signal within 300mV above

Do not leave unused REFCLK inputs floating. Tie either the

true or complement inputs to ground, but not both. A logic zero

is achieved by connecting the complement input to ground

with the true input floating. For a TTL input, tie a 2.5k

Ω resistor

between the complement input and ground. See “Input

Interface” section, Figures 4a through 4j.

Input Levels

LVDS, CML and HSTL differential signals may be connected

directly to the REFCLK inputs. Depending on the actual worst

case voltage seen, the minimum input voltage swing varies as

illustrated in the following table:

Input Voltage Range

Minimum Voltage Swing

0 to 2.4V

100mV

200mV

R2

1.5k

R2

1.5k

R1

1.05k

R1

1.05k

GND

REFCLK

/REFCLK

Figure 3. Simplified Input Structure

Output Logic Characteristics

See

“Output Termination Recommendations” for

illustrations. In cases where single-ended output is desired,

the designer should terminate the unused complimentary

output in the same manner as the normal output that is being

used. Unused LVPECL output pairs can be left floating.

Unused LVDS output pairs should be terminated

w/100

Ω across the pair.

LVPECL operation:

• Typical voltage swing is 700mV

50

Ω.

• Common mode voltage is V

• 100

Ω termination across the output pair is NOT

recommended for LVPECL. See

“Output Termination”

section, Figures 3 to 5.

LVDS operation (SY89535L, Bank B)

• Typical voltage swing is 250mV

effective 50

Ω.

• Common mode voltage is 1.25V, typical.

• 100

Ω termination across differential output pair is

fine.

Thermal Considerations

This part has an exposed die pad for enhanced heat

dissipation. We strongly recommend soldering the exposed

die pad to a ground plane. Where this is not possible, we

recommend maintaining at least 500lfpm air flow around the

part.