5

SY89429V

Micrel, Inc.

M9999-011106

hbwhelp@micrel.com or (408) 955-1690

WITH 16MHZ INPUT

VCO Frequency

256

128

64

32

16

8421

(MHz)

M Count

M8

M7

M6

M5

M4

M3

M2

M1

M0

400

200

011001000

402

201

011001001

404

202

011001010

406

203

011001011

••

•••••••••

••

•••••••••

••

•••••••••

794

397

110001101

796

398

110001110

798

399

110001111

800

400

110010000

The internal oscillator uses the external quartz crystal as the

basis of its frequency reference. The output of the reference

oscillator is divided by eight before being sent to the phase

detector. With a 16MHz crystal, this provides a reference frequency

of 2MHz.

The VCO, within the PLL, operates over a range of 400–

800MHz. Its output is scaled by a divider that is configured by

either the serial or parallel interfaces. The output of this loop

divider is also applied to the phase detector.

The phase detector and loop filter force the VCO output

frequency to be M times the reference frequency by adjusting the

VCO control voltage. Note that for some values of M (either too

high or too low) the PLL will not achieve loop lock. External loop

filter components are utilized to allow for optimal phase jitter

performance.

The output of the VCO is also passed through an output

divider before being sent to the PECL output driver. The output

divider is configured through either the serial or the parallel

interfaces and can provide one of four divider ratios (2, 4, 8 or 16).

This divider extends the performance of the part while providing

a 50% duty cycle.

The output driver is driven differentially from the output divider

and is capable of driving a pair of transmission lines terminated

FUNCTIONAL DESCRIPTION

induced jitter.

The configuration logic has two sections: serial and parallel.

The parallel interface uses the values at the M[8:0] and N[1:0]

inputs to configure the internal counters. Normally, upon

captured. The parallel interface has priority over the serial

interface. Internal pull-up resistors are provided on the M[8:0]

and N[1:0] inputs to reduce component count.

The serial interface logic is implemented with a 14-bit shift

register scheme. The register shifts once per rising edge of the

hold timing as specified in the AC parameters section of this data-

capture the value in the shift register on the HIGH-to-LOW edge

information.

The TEST output reflects various internal node values and is

controlled by the T[2:0] bits in the serial data stream. See the

programming subsection of this data sheet for more information.