A6818SEPTR datasheet(4/7 Pages) ALLEGRO

Part #	A6818SEPTR

Description	DABiC-IV, 32-BIT SERIAL-INPUT, LATCHED SOURCE DRIVER

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Manufacturer	ALLEGRO [Allegro MicroSystems]

Direct Link	http://www.allegromicro.com

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4 / 7 page

6818

32-BIT SERIAL-INPUT,

LATCHED SOURCE DRIVER

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

ELECTRICAL CHARACTERISTICS at TA = +25°C (A6818S-) or over operating temperature

range (A6818E- and A6818K-), VBB = 60 V unless otherwise noted.

Limits @ VDD = 3.3 V Limits @ VDD = 5 V

Characteristic

Symbol

Test Conditions

Mln.

Typ.

Max.

Min.

Typ.

Max.

Units

Output Leakage Current

ICEX

VOUT = 0 V

—

<-0.1

-15

—

<-0.1

-15

µA

Output Voltage

VOUT(1)

IOUT = -25 mA

57.5

58.3

—

57.5

58.3

—

V

VOUT(0)

IOUT = 1 mA

—

1.0

1.5

—

1.0

1.5

V

Output Pull-Down Current

IOUT(0)

VOUT = 5 V to VBB

2.5

5.0

—

2.5

5.0

—

mA

Input Voltage

VIN(1)

2.2

—

3.3

—

V

VIN(0)

—

1.1

—

1.7

V

Input Current

IIN(1)

VIN = VDD

—

<0.01

1.0

—

<0.01

1.0

µA

IIN(0)

VIN = 0.8 V

—

<-0.01

-1.0

—

<-0.01

-1.0

µA

Input Clamp Voltage

VIK

IIN = -200 µA

—

-0.8

-1.5

—

-0.8

-1.5

V

Serial Data Output Voltage

VOUT(1)

IOUT = -200 µA

2.8

3.05

—

4.5

4.75

—

V

VOUT(0)

IOUT = 200 µA

—

0.15

0.3

—

0.15

0.3

V

Maximum Clock Frequency

fc

10

33

—

10

33

—

MHz

Logic Supply Current

IDD(1)

All Outputs High

—

0.25

0.75

—

0.3

1.0

mA

IDD(0)

All Outputs Low

—

0.25

0.75

—

0.3

1.0

mA

Load Supply Current

IBB(1)

All Outputs High, No Load

—

4.5

9.0

—

4.5

9.0

mA

IBB(0)

All Outputs Low

—

0.2

20

—

0.2

20

µA

Blanking-to-Output Delay

tdis(BQ)

CL = 30 pF, 50% to 50%

—

0.7

2.0

—

0.7

2.0

µs

ten(BQ)

CL = 30 pF, 50% to 50%

—

1.8

3.0

—

1.8

3.0

µs

Strobe-to-Output Delay

tp(STH-QL)

RL = 2.3 kΩ, CL ≤ 30 pF

—

0.7

2.0

—

0.7

2.0

µs

tp(STH-QH)

RL = 2.3 kΩ, CL ≤ 30 pF

—

1.8

3.0

—

1.8

3.0

µs

Output Fall Time

tf

RL = 2.3 kΩ, CL ≤ 30 pF

2.4

—

12

2.4

—

12

µs

Output Rise Time

tr

RL = 2.3 kΩ, CL ≤ 30 pF

2.4

—

12

2.4

—

12

µs

Output Slew Rate

dV/dt

RL = 2.3 kΩ, CL ≤ 30 pF

4.0

—

20

4.0

—

20

V/

µs

Clock-to-Serial Data Out Delay tp(CH-SQX)

IOUT = ±200 µA

—

50

—

50

—

ns

Negative current is defined as coming out of (sourcing) the specified device terminal.

Typical data is is for design information only and is at TA = +25°C.

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