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A3992SLP-T Datasheet(PDF) 11 Page - Allegro MicroSystems |
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A3992SLP-T Datasheet(HTML) 11 Page - Allegro MicroSystems |
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11 / 13 page  DMOS Dual Full-Bridge Microstepping PWM Motor Driver A3992 11 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com Terminal List Table Number Name Pin Description B Package LP Package 1 19 VCP Reservoir capacitor terminal 2 20 CP1 Charge pump capacitor terminal 3 21 CP2 Charge pump capacitor terminal 4 22 OUT1B DMOS Full Bridge 1, output B 5 24 VBB1 Load supply 6, 7, 18, 19 7, 18 GND Ground. On B package, internally fused to the die pad for enhanced thermal dissipation. 8 1 SENSE1 Sense resistor terminal for Full Bridge 1 9 2 OUT1A DMOS Full Bridge 1, output A 10 4 STROBE Logic input 11 5 CLOCK Logic input 12 6 DATA Logic input 13 8 REF Gm reference input 14 9 MUX Not used 15 10 VDD Logic supply 16 11 OUT2A DMOS Full Bridge 2, output A 17 12 SENSE2 Sense resistor terminal for Full Bridge 2 20 13 VBB2 Load supply 21 14 OUT2B DMOS Full Bridge 2, output B 22 15 VREG Internal regulator 23 16 SLEEP Logic input 24 17 OSC Oscillator input – 3, 23 NC No connection – – PAD Exposed thermal pad for enhanced thermal dissipation. 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 OSC SLEEP VREG OUT2B VBB2 GND GND SENSE2 OUT2A VDD MUX REF VCP CP1 CP2 OUT1B VBB1 GND GND SENSE1 OUT1A STROBE CLOCK DATA B Package 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VBB1 NC OUT1B CP2 CP1 VCP GND OSC SLEEP VREG OUT2B VBB2 SENSE1 OUT1A NC STROBE CLOCK DATA GND REF MUX VDD OUT2A SENSE2 PAD LP Package Device Pin-out Diagrams |
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