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A3992SLP-T Datasheet(PDF) 7 Page - Allegro MicroSystems |
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A3992SLP-T Datasheet(HTML) 7 Page - Allegro MicroSystems |
7 / 13 page DMOS Dual Full-Bridge Microstepping PWM Motor Driver A3992 7 Allegro MicroSystems, Inc. 115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000 www.allegromicro.com VREG. The VREG pin should be decoupled with a 0.22 μF capacitor to ground. This internally gener- ated supply voltage is used to run the sink side DMOS outputs. VREG is internally monitored and in the case of a fault condition, the outputs of the device are disabled. Current Regulation. The reference voltage can be set by analog input to the REF terminal, or via the internal 2 V precision reference. The choice of reference volt- age and selection of sense resistor set maximum trip current, as follows: ITRIPMAX = VREF/ (Range × RSENSE) . Microstepping current levels are set according to the following equations: ITRIP = VDAC/ (Range × RSENSE) , and VDAC = ((1+DAC) × VREF) / 64 , where DAC is the input code, 1 to 63 (Word 0, D1 to D12), and Range is 4 or 8, as selected by Word 0, D18. Programming a DAC input code to 0 disables the cor- responding bridge, and results in minimum load current. PWM Timer Function. The PWM timer is program- mable via the serial port to provide fixed off-time PWM signals to the control block. In mixed decay mode, the first portion of the off-time operates in fast decay, until the fast decay time count is reached, fol- lowed by slow decay for the remainder of the fixed off-time. If the fast decay time is set longer than the off- time, the device effectively operates in fast decay mode. Oscillator. The PWM timer is based on an oscillator input, typically 4 MHz. The A3992 can be configured to select either the 4 MHz internal oscillator or, if more precise accuracy is required, an external clock can be connected to the OSC terminal. If an external clock is used, 3 internal divider choices are selectable via the serial port to allow flexibility in choosing fOSC based on available system clocks. If the internal oscil- lator option is used, the absolute accuracy is dependent on process variation of resistance and capacitance. A precision resistor can be connected from the OSC terminal to VDD to further improve the tolerance. The frequency is calculated as: fOSC = 204 × 109/ ROSC . If the internal oscillator is used without the external re- sistor the OSC terminal should be connected to GND. D14 – D15 Synchronous Rectification. 2 bits set the different modes of operation (see Synchronous Rectifi- cation in the Functional Description section): D15 D14 Synchronous Rectifier 0 0 Active 0 1 Disabled 1 0 Passive 1 1 Allegro defined use D16, D17 (Reserved). 2 bits reserved for testing. They should be programmed to 0 during normal op- eration. D18 Idle Mode. The device can be put into the low- power Idle mode by writing a 0 to D18. The outputs are disabled, the charge pump turned off, and the de- vice consumes a lower supply current. The undervolt- age monitor circuit remains active. Functional Description |
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