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SY87725LHYTR Datasheet(PDF) 6 Page - Micrel Semiconductor |
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SY87725LHYTR Datasheet(HTML) 6 Page - Micrel Semiconductor |
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6 / 20 page  Micrel, Inc. SY87725L February 2007 6 M9999-021607-A hbwhelp@micrel.com or (408) 955-1690 Functional Description The SY87725L is a fully integrated transceiver with an integrated serial-to-4-bit DeMUX and 4-bit-to-serial Multiplexer. Receive Section Clock and Data Recovery Function The Clock Recovery function includes a synthesizer that generates a stable frequency based on the REFCLK input. The REFCLK input can be either a differential PECL input or a single-ended TTL input. It can also be either 77.76MHz or 155.52MHz as selected by REFFREQSEL. The synthesized frequency derived from the REFCLK is within 1000ppm of the incoming serial data rate and is used by the Clock and Data Recovery (CDR) circuit to “train” to the correct frequency range. This training function minimizes the acquisition time for the CDR to lock onto the incoming data stream by keeping the CDR frequency within close range of the recovered clock in the case of loss of data. The RCV_FSEL0 and RCV_FSEL1 inputs select the receive data rate. For example, these inputs can be used to select an OC-48, OC-24 or OC-12 data rate for the serial data in, SIN. The typical input sensitivity of SIN is 30mV. The Clock Recovery function also generates CLKOUT2 that is controlled by the XMT_DDRSEL input for regular or double data rate applications. If a clean, low-jitter byte-rate clock is not available for CLKIN to the Transmit Synthesizer, CLKOUT2 can be used as the reference clock. DeMUX Function The recovered serial data from the CDR is converted to a 4-bit parallel word by a 1:4 de-multiplexer. The serial- to-parallel conversion sequence is LSB first, i.e. first serial bit in is DOUT0, second serial bit in is DOUT1, etc. A RCV_SYNC pulse input is used to set the word boundary of the 4-bit parallel word. A single pulse, applied asynchronously for a minimum of two input clock cycles to the RCV_SYNC input, causes the start bit of conversion to occur one bit earlier. The CLKOUT output is the parallel data rate clock to be used with the DOUT parallel data from the DeMUX. It is selectable by the RCV_DDRSEL input to be either at the parallel data rate or one-half the parallel data rate for double data rate applications. Transmit Section Synthesizer Function The SY87725L Transmit Synthesizer uses the divide-by- 4 parallel clock input or a divide-by-8 clock input when double data rate is selected as a reference clock. The XMT_FSEL0 and XMT_FSEL1 inputs select the TX data rate. For example, these inputs can be used to select an OC-24, OC-12 or OC-3 rate for the serial data out, SOUT. MUX Function The 4-bit parallel data input is converted to a serial data stream with a 4:1 multiplexer. The parallel-to-serial conversion sequence is LSB first, i.e. DIN0 will be shifted out first, followed by DIN1, etc. Auto-Alignment Function Because the 4-bit parallel data input can have an arbitrary phase relationship with the transmit byte-rate clock input (CLKIN), an auto-alignment function is included in the transmit parallel-to-serial circuit. The phase of the 4-bit parallel data is sampled and compared with the phase of the incoming CLKIN. If the clock and data are not in the proper phase relationship, the phase is internally adjusted to insure that the data will be sampled at the optimal time. This can result in a variation of the latency between the parallel data in and the serial data out (TDOUT) of up to three CLKIN clock cycles. Loopback Function Two 3:1 multiplexers are provided to allow Local or Remote Loopback. |
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