SY87700L

3

Micrel, Inc.

M9999-111406

hbwhelp@micrel.com or (408) 955-1690

Pin Number

Pin Number

SOIC

TQFP

Pin Name

Pin Function

42

RDINP,

Serial Data Input (Differential PECL): These built-in line receiver inputs are

53

RDINN

connected to the differential receive serial data stream. An internal receive

PLL recovers the embedded clock (RCLK) and data (RDOUT) information.

The incoming data rate can be within one of five frequency ranges depend-

ing on the state of the FREQSEL pins. See “Frequency Selection” table.

75

REFCLK

Reference Clock (TTL Inputs): This input is used as the reference for the

internal frequency synthesizer and the “training” frequency for the receiver

PLL to keep it centered in the absence of data coming in on the RDIN inputs.

27

26

CD

Carrier Detect (PECL Input): This input controls the recovery function of the

Receive PLL and can be driven by the carrier detect output of optical

modules or from external transition detection circuitry. When this input is

HIGH the input data stream (RDIN) is recovered normally by the Receive

PLL. When this input is LOW the data on the inputs RDIN will be internally

forced to a constant LOW, the data outputs RDOUT will remain LOW, the

Link Fault Indicator output LFIN forced LOW and the clock recovery PLL

forced to look onto the clock frequency generated from REFCLK.

64

FREQSEL1,

Frequency Select (TTL Inputs): These inputs select the output clock

86

FREQSEL2,

frequency range as shown in the “Frequency Selection” table.

97

FREQSEL3

332

DIVSEL1,

Divider Select (TTL Inputs): These inputs select the ratio between the

26

25

DIVSEL2

output clock frequency (RCLK/TCLK) and the REFCLK input frequency as

shown in the “Reference Frequency Selection” table.

17

16

CLKSEL

Clock Select (TTL Inputs): This input is used to select either the recovered

clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency

synthesizer (CLKSEL = LOW) to the TCLK outputs.

231

LFIN

Link Fault Indicator (TTL Output): This output indicates the status of the

input data stream RDIN. Active HIGH signal is indicating when the internal

clock recovery PLL has locked onto the incoming data stream. LFIN will go

HIGH if CD is HIGH and RDIN is within the frequency range of the Receive

PLL (1000ppm). LFIN is an asynchronous output.

25

24

RDOUTP,

Receive Data Output (Differential PECL): These ECL 100k outputs

24

23

RDOUTN

represent the recovered data from the input data stream (RDIN). This

recovered data is specified against the rising edge of RCLK.

22

21

RCLKP,

Clock Output (Differential PECL): These ECL 100k outputs represent the

21

20

RCLKN

recovered clock used to sample the recovered data (RDOUT).

19

18

TCLKP,

Clock Output (Differential PECL): These ECL 100k outputs represent

18

17

TCLKN

either the recovered clock (CLKSEL = HIGH) used to sample the recovered

data (RDOUT) or the transmit clock of the frequency synthesizer

(CLKSEL = LOW).

11

9

PLLSP,

Clock Synthesis PLL Loop Filter. External loop filter pins for the clock

12

10

PLLSN

synthesis PLL.

16

15

PLLRP,

Clock Recovery PLL Loop Filter. External loop filter pins for the receiver

15

14

PLLRN

PLL.

27, 28,

1

29, 30

20, 23

19, 22

13, 14

12, 13

GND

Ground

10

1, 8

NC

No Connect

Note:

1. V

PIN DESCRIPTIONS