SY58604UMGTR datasheet(5/13 Pages) MICREL

Part #	SY58604UMGTR

Description	3.2Gbps Precision, LVPECL Buffer with Internal Termination and Fail Safe Input

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Manufacturer	MICREL [Micrel Semiconductor]

Direct Link	http://www.micrel.com

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Micrel, Inc.

SY58604U

September 2006

5

M9999-092606-A

hbwhelp@micrel.com or (408) 955-1690

AC Electrical Characteristics

VCC = +2.5V ±5% or +3.3V ±10%, RL = 50Ω to VCC-2V, Input tr/tf: <300ps; TA = –40°C to +85°C, unless otherwise

stated.

Symbol

Parameter

Condition

Min

Typ

Max

Units

NRZ Data

3.2

4.25

Gbps

fMAX

Maximum Frequency

VOUT > 400mV

Clock

2.5

3

GHz

VIN: 100mV-200mV

180

320

450

ps

tPD

Propagation Delay

IN-to-Q

VIN: 200mV-800mV

150

230

350

ps

tSkew

Part-to-Part Skew

Note 7

135

ps

Data

Random Jitter

Note 8

1

psRMS

Deterministic Jitter

Note 9

10

psPP

Clock

Cycle-to-Cycle Jitter

Note 10

1

psRMS

tJitter

Total Jitter

Note 11

10

psPP

tr, tf

Output Rise/Fall Times

(20% to 80%)

At full output swing.

40

75

110

ps

Duty Cycle

Differential I/O

47

53

%

Notes:

7.

Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no skew at the edges at the

respective inputs.

8.

Random jitter is measured with a K28.7 pattern, measured at ≤ fMAX.

9.

Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2

23–1 PRBS pattern.

10. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1,

where T is the time between rising edges of the output signal.

11. Total jitter definition: with an ideal clock input frequency of ≤ fMAX (device), no more than one output edge in 10

12 output edges will deviate by

more than the specified peak-to-peak jitter value.

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