5

4707B–AUTO–10/05

U6808B

5.5

RESET Input

During power-on and under/overvoltage detection a reset signal is fed to this pin. It resets the

watchdog timer and sets the initial state.

5.6

WD-OK Output

After the up/down counter is incremented to status 3 (see Figure 5-2) the RS flip-flop is set and

the WD-OK output becomes logic 1. This information is available for the microcontroller at the

open-collector output ENABLE. If on the other hand the up/down counter is decremented to 0

the RS flip-flop is reset, the WD-OK output and the ENABLE output are disabled. The WD-OK

output also controls a dual MUX stage which shifts the time window by one clock after a suc-

cessful trigger, thus forming a hysteresis to provide stable conditions for the evaluation of the

trigger signal good or false. The WD-OK signal is also reset in case the watchdog counter is not

reset after 250 clocks (missing trigger signal).

5.7

Watchdog State Diagram

Figure 5-2.

Watchdog State Diagram

5.8

Explanation

In each block, the first character represents the state of the counter. The second notation indi-

cates the fault status of the counter. A fault status is indicated by an F and a no fault status is

indicated by an NF. When the watchdog is powered up initially, the counter starts out at the 0/F

block (initial state). Good indicates that a pulse has been received whose width resides within

the timing window. Bad indicates that a pulse has been received whose width is either too short

or too long.

1/NF

2/NF

O/F

1/F

2/F

3/NF

bad

good

bad

good

bad

good

good

bad

good

good

bad

bad

Initial status