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AAT1110IJS-0.6-T1 Datasheet(PDF) 10 Page - Advanced Analogic Technologies |
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AAT1110IJS-0.6-T1 Datasheet(HTML) 10 Page - Advanced Analogic Technologies |
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10 / 19 page  AAT1110 Fast Transient 800mA Step-Down Converter 10 1110.2006.04.1.0 Control Loop The AAT1110 is a peak current mode step-down converter. The current through the P-channel MOSFET (high side) is sensed for current loop control, as well as short circuit and overload pro- tection. A fixed slope compensation signal is added to the sensed current to maintain stability for duty cycles greater than 50%. The peak current mode loop appears as a voltage-programmed current source in parallel with the output capacitor. The output of the voltage error amplifier programs the current mode loop for the necessary peak switch current to force a constant output voltage for all load and line conditions. Internal loop compen- sation terminates the transconductance voltage error amplifier output. For fixed voltage versions, the error amplifier reference voltage is internally set to program the converter output voltage. For the adjustable output, the error amplifier reference is fixed at 0.6V. Soft Start / Enable Soft start limits the current surge seen at the input and eliminates output voltage overshoot. When pulled low, the enable input forces the AAT1110 into a low-power, non-switching state. The total input current during shutdown is less than 1µA. Current Limit and Over-Temperature Protection For overload conditions, the peak input current is limited. To minimize power dissipation and stresses under current limit and short-circuit conditions, switching is terminated after entering current limit for a series of pulses. Switching is terminated for seven consecutive clock cycles after a current limit has been sensed for a series of four consecutive clock cycles. Thermal protection completely disables switching when internal dissipation becomes excessive. The junction over-temperature threshold is 140°C with 15°C of hysteresis. Once an over-temperature or over-current fault conditions is removed, the output voltage automatically recovers. Under-Voltage Lockout Internal bias of all circuits is controlled via the VIN input. Under-voltage lockout (UVLO) guarantees sufficient VIN bias and proper operation of all inter- nal circuitry prior to activation. Figure 1: Enhanced Transient Response Schematic. L1 CDRH3D16-4R7 4.7 μH L1 10 μF C1 4.7 μF C2 U1 AAT1110 SC70JW-8 C2 4.7 μF 10V 0805 X5R V OUT =1.8V GND V IN 1 2 3 Enable LX EN 1 OUT 2 VIN 3 LX 4 AGND 5 PGND 6 PGND 7 PGND 8 AAT1110 U1 GND2 118k R1 59k R2 C1 10 μF 6.3V 0805 X5R 100pF C4 n/a C3 |
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