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SY100H607JCTR Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY100H607JCTR Datasheet(HTML) 1 Page - Micrel Semiconductor |
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1 / 5 page  1 SY10H607 SY100H607 Micrel, Inc. M9999-032906 hbwhelp@micrel.com or (408) 955-1690 DESCRIPTION FEATURES s Differential PECL data and clock inputs s 48mA sink, 15mA source TTL outputs s Single +5V power supply s Multiple power and ground pins to minimize noise s Specified within-device skew s VBB output for single-ended use s Fully compatible with MC10H/100H607 s Available in 28-pin PLCC package The SY10/100H607 are 6-bit, registered, dual supply PECL-to-TTL translators. The devices feature differential PECL inputs for both data and clock. The TTL outputs feature 48mA sink, 15mA source drive capability for driving high fanout loads. The asynchronous master reset control is a PECL level input. With its differential PECL inputs and TTL outputs, the H607 device is ideally suited for the receive function of a HPPI bus-type board-to-board interface application. The on-chip registers simplify the task of synchronizing the data between the two boards. The device is available in either ECL standard: the 10H device is compatible with 10K logic levels, while the 100H device is compatible with 100K logic levels. BLOCK DIAGRAM SY10H607 SY100H607 Rev.: G Amendment: /0 Issue Date: March 2006 DQ R CLK Dn CLK CLK Qn MR VBB 1 OF 6 BITS Dn REGISTERED HEX PECL-TO-TTL Pin Function D0 – D5 True PECL Data Inputs D0 – D5 Inverted PECL Data Inputs CLK, CLK Differential PECL Clock Input MR PECL Master Reset Input Q0 – Q5 TTL Outputs VCCE PECL VCC (5.0V) VCCT TTL VCC (5.0V) TGND TTL Ground EGND PECL Ground VBB VBB Reference Output (PECL) PIN NAMES |
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