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3946 Datasheet(PDF) 11 Page - Allegro MicroSystems |
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3946 Datasheet(HTML) 11 Page - Allegro MicroSystems |
11 / 13 page 11 Worcester, Massachusetts 01615-0036 (508) 853-5000 115 Northeast Cutoff, Box 15036 www.allegromicro.com 3946 Half-Bridge Power MOSFET Controller Pin Name Pin Description SOIC-16 (A3946KLB) TSSOP-16 (A3946KLP) VREG Gate drive supply. 1 1 CP2 Charge pump capacitor, positive side. When not using the charge pump, leave this pin open. 22 CP1 Charge pump capacitor, negative side. When not using the charge pump, leave this pin open. 33 PGND* External ground. Internally connected to the power ground. 4 4 GL Low-side gate drive output for external MOSFET driver. External series gate resistor can be used to control slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of the S pin output. 55 S Directly connected to the load terminal. The pin is also connected to the negative side of the bootstrap capacitor and negative supply connection for the floating high-side drive. 66 GH High-side gate drive output for N-channel MOSFET driver. External series gate resistor can be used to control slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of the S pin output. 77 BOOT High-side connection for bootstrap capacitor, positive supply for the high-side gate drive. 88 ~FAULT Diagnostic output, open drain. Low during a fault condition. 9 9 IN1 Logic control. 10 10 IN2 Logic control. 11 11 RESET Logic control input. When RESET = 0, the chip is in a very low power sleep mode. 12 12 LGND* External ground. Internally connected to the logic ground. 13 13 DT Dead Time. Connecting a resistor to GND sets the turn-on delay to prevent shoot-through. Forcing this input high disables the dead time circuit and changes the logic truth table. 14 14 VREF 5 V internal reference decoupling terminal. 15 15 VBB Supply Input. 16 16 *In the LB package, the PGND pin (4) and LGND pin (13) grounds are internally connected by the leadframe. In the LP package, however, the PGND pin (4) and LGND pin (13) grounds are NOT internally connected, and both must be connected to ground externally. In the LP package, the exposed thermal pad is not connected to any pin, but should be externally connected to ground, to reduce noise pickup by the pad. |
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Similar Description - 3946_04 |
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