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MC68HC705B5 Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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MC68HC705B5 Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
10 / 302 page Freescale ii MC68HC05B6 Rev. 4.1 TABLE OF CONTENTS Paragraph Number Page Number TABLE OF CONTENTS 2.5.13 PLMB ......................................................................................................... 2–13 2.5.14 VPP1.......................................................................................................... 2–13 2.5.15 VRH ........................................................................................................... 2–13 2.5.16 VRL............................................................................................................ 2–13 2.5.17 PA0 – PA7/PB0 – PB7/PC0 – PC7 ............................................................ 2–13 2.5.18 PD0/AN0–PD7/AN7................................................................................... 2–13 3 MEMORY AND REGISTERS 3.1 Registers ........................................................................................................... 3–1 3.2 RAM .................................................................................................................. 3–1 3.3 ROM .................................................................................................................. 3–1 3.4 Self-check ROM ................................................................................................ 3–2 3.5 EEPROM ........................................................................................................... 3–3 3.5.1 EEPROM control register ............................................................................ 3–3 3.5.2 EEPROM read operation ............................................................................. 3–5 3.5.3 EEPROM erase operation ........................................................................... 3–5 3.5.4 EEPROM programming operation ............................................................... 3–6 3.5.5 Options register (OPTR) .............................................................................. 3–6 3.6 EEPROM during STOP mode ........................................................................... 3–7 3.7 EEPROM during WAIT mode ............................................................................ 3–7 3.8 Miscellaneous register...................................................................................... 3–9 4 INPUT/OUTPUT PORTS 4.1 Input/output programming ................................................................................. 4–1 4.2 Ports A and B .................................................................................................... 4–2 4.3 Port C ................................................................................................................ 4–3 4.4 Port D ................................................................................................................ 4–3 4.5 Port registers ..................................................................................................... 4–4 4.5.1 Port data registers A and B (PORTA and PORTB) ...................................... 4–4 4.5.2 Port data register C (PORTC)...................................................................... 4–4 4.5.3 Port data register D (PORTD)...................................................................... 4–5 4.5.3.1 A/D status/control register...................................................................... 4–5 4.5.4 Data direction registers (DDRA, DDRB and DDRC).................................... 4–5 4.6 Other port considerations .................................................................................. 4–6 |
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