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SY100E171JZTR Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY100E171JZTR Datasheet(HTML) 1 Page - Micrel Semiconductor |
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1 / 4 page  1 SY10E171 SY100E171 Micrel, Inc. M9999-032006 hbwhelp@micrel.com or (408) 955-1690 s 725ps max. D to output s Extended 100E VEE range of –4.2V to –5.5V s Differential outputs s Split select architecture s Fully compatible with industry standard 10KH, 100K ECL levels s Internal 75K Ω input pulldown resistors s Fully compatible with Motorola MC10E/100E171 s Available in 28-pin PLCC package FEATURES 3-BIT 4:1 MULTIPLEXER The SY10/100E171 offer three 4:1 multiplexers with differential outputs, designed for use in new, high- performance ECL systems. The leading 4-bit multiplexer operation is organized pairwise, with each pair being a 2- bit multiplexer. Separate select (SEL1A, SEL1B) controls are provided within each pair. The SEL1A and SEL1B signals control the leading multiplexers, while the SEL2 signal controls the output multiplexer. The three select signals can be used to determine which of the four data inputs will be propagated to the corresponding outputs. DESCRIPTION SY10E171 SY100E171 BLOCK DIAGRAM Pin Function D0x–D2x Data Inputs SEL1A, SEL1B First-stage Select Inputs SEL2 Second-stage Select Input Q0–Q2 True Output Q0–Q2 Inverted Output VCCO VCC to Output PIN NAMES MUX SEL 2:1 Q0 Q0 Q1 Q1 Q2 Q2 D0a D0b SEL1A D0c D0d D1a D1b D1c D1d D2a D2b D2c D2d SEL1B SEL2 MUX SEL 2:1 MUX SEL 2:1 MUX SEL 2:1 MUX SEL 2:1 MUX SEL 2:1 MUX SEL 2:1 MUX SEL 2:1 MUX SEL 2:1 Rev.: E Amendment: /0 Issue Date: March 2006 |
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